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[AMD Official Use Only - AMD Internal Distribution Only]<br>
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We could clean that up, but if we did so, we should add a second switch statement for the userq_funcs assignments so we can enable them selectively as the firmwares become available.</div>
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Alex</div>
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<div id="divRplyFwdMsg" dir="ltr"><span style="font-family: Calibri, sans-serif; font-size: 11pt; color: rgb(0, 0, 0);"><b>From:</b> Khatri, Sunil <Sunil.Khatri@amd.com><br>
<b>Sent:</b> Wednesday, March 26, 2025 11:36 AM<br>
<b>To:</b> Deucher, Alexander <Alexander.Deucher@amd.com>; amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org><br>
<b>Cc:</b> Deucher, Alexander <Alexander.Deucher@amd.com><br>
<b>Subject:</b> RE: [PATCH 1/2] drm/amdgpu/gfx11: fix num_mec</span>
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<div style="font-family: "Times New Roman"; font-size: 11pt;">[AMD Official Use Only - AMD Internal Distribution Only]<br>
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Gfx11 now we have same values, hence we don’t need to differentiate between two sets , only one set is needed like below.<br>
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As below<br>
case IP_VERSION(11, 0, 0):<br>
case IP_VERSION(11, 0, 2):<br>
case IP_VERSION(11, 0, 3):<br>
case IP_VERSION(11, 0, 1):<br>
case IP_VERSION(11, 0, 4):<br>
case IP_VERSION(11, 5, 0):<br>
case IP_VERSION(11, 5, 1):<br>
case IP_VERSION(11, 5, 2):<br>
case IP_VERSION(11, 5, 3):<br>
adev->gfx.me.num_me = 1;<br>
adev->gfx.me.num_pipe_per_me = 1;<br>
adev->gfx.me.num_queue_per_pipe = 1;<br>
adev->gfx.mec.num_mec = 1;<br>
adev->gfx.mec.num_pipe_per_mec = 4;<br>
adev->gfx.mec.num_queue_per_pipe = 4;<br>
#ifdef CONFIG_DRM_AMDGPU_NAVI3X_USERQ<br>
adev->userq_funcs[AMDGPU_HW_IP_GFX] = &userq_mes_funcs;<br>
adev->userq_funcs[AMDGPU_HW_IP_COMPUTE] = &userq_mes_funcs;<br>
#endif<br>
break;<br>
<br>
Regards<br>
Sunil Khatri<br>
<br>
-----Original Message-----<br>
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Alex Deucher<br>
Sent: Wednesday, March 26, 2025 7:13 PM<br>
To: amd-gfx@lists.freedesktop.org<br>
Cc: Deucher, Alexander <Alexander.Deucher@amd.com><br>
Subject: [PATCH 1/2] drm/amdgpu/gfx11: fix num_mec<br>
<br>
GC11 only has 1 mec.<br>
<br>
Fixes: 3d879e81f0f9 ("drm/amdgpu: add init support for GFX11 (v2)")<br>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com><br>
---<br>
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 2 +-<br>
1 file changed, 1 insertion(+), 1 deletion(-)<br>
<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c<br>
index e0a9b10d645c6..a9ef33205c541 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c<br>
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c<br>
@@ -1573,7 +1573,7 @@ static int gfx_v11_0_sw_init(struct amdgpu_ip_block *ip_block)<br>
adev->gfx.me.num_me = 1;<br>
adev->gfx.me.num_pipe_per_me = 1;<br>
adev->gfx.me.num_queue_per_pipe = 1;<br>
- adev->gfx.mec.num_mec = 2;<br>
+ adev->gfx.mec.num_mec = 1;<br>
adev->gfx.mec.num_pipe_per_mec = 4;<br>
adev->gfx.mec.num_queue_per_pipe = 4; #ifdef CONFIG_DRM_AMDGPU_NAVI3X_USERQ<br>
--<br>
2.49.0<br>
<br>
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