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[AMD Official Use Only - AMD Internal Distribution Only]<br>
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<div dir="ltr">Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> </div>
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<div dir="ltr">Regards,</div>
<div dir="ltr">Hawking</div>
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<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> amd-gfx <amd-gfx-bounces@lists.freedesktop.org> on behalf of Tao Zhou <tao.zhou1@amd.com><br>
<b>Sent:</b> Thursday, April 3, 2025 2:48:12 PM<br>
<b>To:</b> amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org><br>
<b>Cc:</b> Zhou1, Tao <Tao.Zhou1@amd.com><br>
<b>Subject:</b> [PATCH] drm/amdgpu: add loop bits for NPS2 RAS page retirement</font>
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<div class="BodyFragment"><font size="2"><span style="font-size:11pt;">
<div class="PlainText">Support NPS2 UMC RAS.<br>
<br>
Signed-off-by: Tao Zhou <tao.zhou1@amd.com><br>
---<br>
drivers/gpu/drm/amd/amdgpu/umc_v12_0.c | 10 ++++++++++<br>
drivers/gpu/drm/amd/amdgpu/umc_v12_0.h | 2 ++<br>
2 files changed, 12 insertions(+)<br>
<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v12_0.c b/drivers/gpu/drm/amd/amdgpu/umc_v12_0.c<br>
index 0e404c074975..da00d6b3b6a3 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/umc_v12_0.c<br>
+++ b/drivers/gpu/drm/amd/amdgpu/umc_v12_0.c<br>
@@ -220,6 +220,13 @@ static int umc_v12_0_convert_error_address(struct amdgpu_device *adev,<br>
nps = adev->gmc.gmc_funcs->query_mem_partition_mode(adev);<br>
<br>
/* other nps modes are taken as nps1 */<br>
+ if (nps == AMDGPU_NPS2_PARTITION_MODE) {<br>
+ loop_bits[0] = UMC_V12_0_PA_CH5_BIT;<br>
+ loop_bits[1] = UMC_V12_0_PA_C2_BIT;<br>
+ loop_bits[2] = UMC_V12_0_PA_B1_BIT;<br>
+ loop_bits[3] = UMC_V12_0_PA_R12_BIT;<br>
+ }<br>
+<br>
if (nps == AMDGPU_NPS4_PARTITION_MODE) {<br>
loop_bits[0] = UMC_V12_0_PA_CH4_BIT;<br>
loop_bits[1] = UMC_V12_0_PA_CH5_BIT;<br>
@@ -517,6 +524,9 @@ static int umc_v12_0_update_ecc_status(struct amdgpu_device *adev,<br>
<br>
if (adev->gmc.gmc_funcs->query_mem_partition_mode)<br>
nps = adev->gmc.gmc_funcs->query_mem_partition_mode(adev);<br>
+<br>
+ if (nps == AMDGPU_NPS2_PARTITION_MODE)<br>
+ shift_bit = UMC_V12_0_PA_B1_BIT;<br>
if (nps == AMDGPU_NPS4_PARTITION_MODE)<br>
shift_bit = UMC_V12_0_PA_B0_BIT;<br>
<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v12_0.h b/drivers/gpu/drm/amd/amdgpu/umc_v12_0.h<br>
index 9298018d938f..056bbc038312 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/umc_v12_0.h<br>
+++ b/drivers/gpu/drm/amd/amdgpu/umc_v12_0.h<br>
@@ -65,12 +65,14 @@<br>
/* row bits in SOC physical address */<br>
#define UMC_V12_0_PA_R0_BIT 22<br>
#define UMC_V12_0_PA_R11_BIT 33<br>
+#define UMC_V12_0_PA_R12_BIT 34<br>
#define UMC_V12_0_PA_R13_BIT 35<br>
/* channel bit in SOC physical address */<br>
#define UMC_V12_0_PA_CH4_BIT 12<br>
#define UMC_V12_0_PA_CH5_BIT 13<br>
/* bank bit in SOC physical address */<br>
#define UMC_V12_0_PA_B0_BIT 19<br>
+#define UMC_V12_0_PA_B1_BIT 20<br>
/* row bits in MCA address */<br>
#define UMC_V12_0_MA_R0_BIT 10<br>
<br>
-- <br>
2.34.1<br>
<br>
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