<html xmlns:v="urn:schemas-microsoft-com:vml" xmlns:o="urn:schemas-microsoft-com:office:office" xmlns:w="urn:schemas-microsoft-com:office:word" xmlns:m="http://schemas.microsoft.com/office/2004/12/omml" xmlns="http://www.w3.org/TR/REC-html40"> <head> <meta http-equiv="Content-Type" content="text/html; charset=us-ascii"> <meta name="Generator" content="Microsoft Word 15 (filtered medium)"> <style></style> </head> <body lang="EN-US" link="#467886" vlink="#96607D" style="word-wrap:break-word"> [Public] <div> <div class="WordSection1"> In theory , I don’t see the problem to use kiq to reset the schq. But I think it’s more stable to let driver do the reset for both kiq and schq since these two queues are the basic part for others parts to run normally . <o:p></o:p> <o:p> </o:p> Regards<o:p></o:p> Shaoyun.liu<o:p></o:p> <o:p> </o:p> <div> <div style="border:none;border-top:solid #E1E1E1 1.0pt;padding:3.0pt 0in 0in 0in"> From: Chen, Michael <Michael.Chen@amd.com> Sent: Thursday, May 8, 2025 2:32 PM To: Deucher, Alexander <Alexander.Deucher@amd.com>; amd-gfx@lists.freedesktop.org Cc: Liu, Shaoyun <Shaoyun.Liu@amd.com> Subject: Re: [PATCH] drm/amdgpu/mes12: rework pipe selection for legacy queues<o:p></o:p> </div> </div> <o:p> </o:p> [Public]<o:p></o:p> <o:p> </o:p> <div> <div> <o:p> </o:p> </div> <div> <o:p> </o:p> </div> <div class="MsoNormal" align="center" style="text-align:center"> <hr size="2" width="98%" align="center"> </div> <div id="divRplyFwdMsg"> From: Deucher, Alexander <<a href="mailto:Alexander.Deucher@amd.com">Alexander.Deucher@amd.com</a>> Sent: Thursday, May 8, 2025 1:24 PM To: <a href="mailto:amd-gfx@lists.freedesktop.org">amd-gfx@lists.freedesktop.org</a> <<a href="mailto:amd-gfx@lists.freedesktop.org">amd-gfx@lists.freedesktop.org</a>> Cc: Deucher, Alexander <<a href="mailto:Alexander.Deucher@amd.com">Alexander.Deucher@amd.com</a>>; Chen, Michael <<a href="mailto:Michael.Chen@amd.com">Michael.Chen@amd.com</a>>; Liu, Shaoyun <<a href="mailto:Shaoyun.Liu@amd.com">Shaoyun.Liu@amd.com</a>> Subject: [PATCH] drm/amdgpu/mes12: rework pipe selection for legacy queues <o:p></o:p> <div> <o:p></o:p> </div> </div> <div> Only use the KIQ pipe for the scheduler queue. For legacy kernel queues, use the scheduler pipe. This aligns with mes11. Cc: Michael Chen <<a href="mailto:Michael.Chen@amd.com">Michael.Chen@amd.com</a>> Cc: Shaoyun Liu <<a href="mailto:Shaoyun.Liu@amd.com">Shaoyun.Liu@amd.com</a>> Signed-off-by: Alex Deucher <<a href="mailto:alexander.deucher@amd.com">alexander.deucher@amd.com</a>> --- drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 11 ++++++++++- drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h | 4 +++- drivers/gpu/drm/amd/amdgpu/mes_v12_0.c | 18 +++++++++--------- 3 files changed, 22 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c index 2febb63ab2322..f665daf71780d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c @@ -299,6 +299,9 @@ int amdgpu_mes_map_legacy_queue(struct amdgpu_device *adev, queue_input.queue_id = ring->queue; queue_input.mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); queue_input.wptr_addr = ring->wptr_gpu_addr; + /* need to use KIQ pipe to map the scheduler queue */ + if (ring == &adev->mes.ring[AMDGPU_MES_SCHED_PIPE]) + queue_input.use_kiq = true; r = adev->mes.funcs->map_legacy_queue(&adev->mes, &queue_input); if (r) @@ -323,6 +326,10 @@ int amdgpu_mes_unmap_legacy_queue(struct amdgpu_device *adev, queue_input.trail_fence_addr = gpu_addr; queue_input.trail_fence_data = seq; + /* need to use KIQ pipe to unmap the scheduler queue */ + if (ring == &adev->mes.ring[AMDGPU_MES_SCHED_PIPE]) + queue_input.use_kiq = true; + r = adev->mes.funcs->unmap_legacy_queue(&adev->mes, &queue_input); if (r) DRM_ERROR("failed to unmap legacy queue\n"); @@ -349,7 +356,9 @@ int amdgpu_mes_reset_legacy_queue(struct amdgpu_device *adev, queue_input.wptr_addr = ring->wptr_gpu_addr; queue_input.vmid = vmid; queue_input.use_mmio = use_mmio; - queue_input.is_kq = true; + /* need to use KIQ pipe to reset the scheduler queue */ + if (ring == &adev->mes.ring[AMDGPU_MES_SCHED_PIPE]) + queue_input.use_kiq = true; if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) queue_input.legacy_gfx = true;<o:p></o:p> </div> <div> We are not supposed to reset scheduler queue, so this change is not necessary. <o:p></o:p> </div> <div> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h index a41f65b4f733a..d1836ad93ccfe 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h @@ -242,6 +242,7 @@ struct mes_map_legacy_queue_input { uint32_t queue_id; uint64_t mqd_addr; uint64_t wptr_addr; + bool use_kiq; }; struct mes_unmap_legacy_queue_input { @@ -252,6 +253,7 @@ struct mes_unmap_legacy_queue_input { uint32_t queue_id; uint64_t trail_fence_addr; uint64_t trail_fence_data; + bool use_kiq; }; struct mes_suspend_gang_input { @@ -277,7 +279,7 @@ struct mes_reset_queue_input { uint64_t wptr_addr; uint32_t vmid; bool legacy_gfx; - bool is_kq; + bool use_kiq; }; enum mes_misc_opcode { diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c index b4f17332d4664..8f2e24ecf747f 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c @@ -515,7 +515,7 @@ static int mes_v12_0_map_legacy_queue(struct amdgpu_mes *mes, convert_to_mes_queue_type(input->queue_type); mes_add_queue_pkt.map_legacy_kq = 1; - if (mes->adev->enable_uni_mes) + if (input->use_kiq) pipe = AMDGPU_MES_KIQ_PIPE; else pipe = AMDGPU_MES_SCHED_PIPE; @@ -554,7 +554,7 @@ static int mes_v12_0_unmap_legacy_queue(struct amdgpu_mes *mes, convert_to_mes_queue_type(input->queue_type); } - if (mes->adev->enable_uni_mes) + if (input->use_kiq) pipe = AMDGPU_MES_KIQ_PIPE; else pipe = AMDGPU_MES_SCHED_PIPE; @@ -869,7 +869,7 @@ static int mes_v12_0_reset_hw_queue(struct amdgpu_mes *mes, mes_reset_queue_pkt.doorbell_offset = input->doorbell_offset; } - if (input->is_kq) + if (input->use_kiq) pipe = AMDGPU_MES_KIQ_PIPE; else pipe = AMDGPU_MES_SCHED_PIPE; @@ -1339,7 +1339,7 @@ static int mes_v12_0_kiq_enable_queue(struct amdgpu_device *adev) return r; } - kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring[0]); + kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring[AMDGPU_MES_SCHED_PIPE]); r = amdgpu_ring_test_ring(kiq_ring); if (r) { @@ -1608,7 +1608,7 @@ static void mes_v12_0_kiq_dequeue_sched(struct amdgpu_device *adev) soc21_grbm_select(adev, 0, 0, 0, 0); mutex_unlock(&adev->srbm_mutex); - adev->mes.ring[0].sched.ready = false; + adev->mes.ring[AMDGPU_MES_SCHED_PIPE].sched.ready = false; } static void mes_v12_0_kiq_setting(struct amdgpu_ring *ring) @@ -1687,7 +1687,7 @@ static int mes_v12_0_kiq_hw_init(struct amdgpu_device *adev) static int mes_v12_0_kiq_hw_fini(struct amdgpu_device *adev) { - if (adev->mes.ring[0].sched.ready) { + if (adev->mes.ring[AMDGPU_MES_SCHED_PIPE].sched.ready) { if (adev->enable_uni_mes) amdgpu_mes_unmap_legacy_queue(adev, &adev->mes.ring[AMDGPU_MES_SCHED_PIPE], @@ -1695,7 +1695,7 @@ static int mes_v12_0_kiq_hw_fini(struct amdgpu_device *adev) else mes_v12_0_kiq_dequeue_sched(adev); - adev->mes.ring[0].sched.ready = false; + adev->mes.ring[AMDGPU_MES_SCHED_PIPE].sched.ready = false; } mes_v12_0_enable(adev, false); @@ -1708,7 +1708,7 @@ static int mes_v12_0_hw_init(struct amdgpu_ip_block *ip_block) int r; struct amdgpu_device *adev = ip_block->adev; - if (adev->mes.ring[0].sched.ready) + if (adev->mes.ring[AMDGPU_MES_SCHED_PIPE].sched.ready) goto out; if (!adev->enable_mes_kiq) { @@ -1763,7 +1763,7 @@ static int mes_v12_0_hw_init(struct amdgpu_ip_block *ip_block) * with MES enabled. */ adev->gfx.kiq[0].ring.sched.ready = false; - adev->mes.ring[0].sched.ready = true; + adev->mes.ring[AMDGPU_MES_SCHED_PIPE].sched.ready = true; return 0; -- 2.49.0<o:p></o:p> </div> </div> </div> </div> </body> </html>