<div><p style="font-size:50px;margin-top:0;margin-bottom:0">👍</p><p style="margin-top:10px;margin-bottom:0">Sebastian reagiu pelo <a style="color:unset;text-decoration:underline" href="https://www.google.com/gmail/about/?utm_source=gmail-in-product&utm_medium=et&utm_campaign=emojireactionemail#app">Gmail</a></p></div><br><div class="gmail_quote gmail_quote_container"><div dir="ltr" class="gmail_attr">Em sex., 9 de mai. de 2025, 20:59, Alex Hung <<a href="mailto:alex.hung@amd.com">alex.hung@amd.com</a>> escreveu:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Reviewed-by: Alex Hung <<a href="mailto:alex.hung@amd.com" target="_blank" rel="noreferrer">alex.hung@amd.com</a>><br>
<br>
On 5/5/25 12:20, Alex Hung wrote:<br>
> Thanks. I will send this patch for testing.<br>
> <br>
> Note I still see a warning of mismatch of author and SOB as below, but <br>
> that can be fixed to "Sebastian Aguilera Novoa <<a href="mailto:saguileran@ime.usp.br" target="_blank" rel="noreferrer">saguileran@ime.usp.br</a>>" <br>
> manually after testing and before merging.<br>
> <br>
> $ ./scripts/<a href="http://checkpatch.pl" rel="noreferrer noreferrer" target="_blank">checkpatch.pl</a> v2-drm-amd-display-dc-irq-Remove-duplications- <br>
> of-hpd_ack-function-from-IRQ.patch.patch<br>
> WARNING: From:/Signed-off-by: email address mismatch: 'From: Sebastian <br>
> Aguilera Novoa <<a href="mailto:saguileranbr@gmail.com" target="_blank" rel="noreferrer">saguileranbr@gmail.com</a>>' != 'Signed-off-by: Sebastian <br>
> Aguilera Novoa <<a href="mailto:saguileran@ime.usp.br" target="_blank" rel="noreferrer">saguileran@ime.usp.br</a>>'<br>
> <br>
> total: 0 errors, 1 warnings, 740 lines checked<br>
> <br>
> <br>
> On 5/2/25 21:59, Sebastian Aguilera Novoa wrote:<br>
>> The major of dcn and dce irqs share a copy-pasted collection<br>
>> of copy-pasted function, which is: hpd_ack.<br>
>><br>
>> This patch removes the multiple copy-pasted by moving them to<br>
>> the irq_service.c and make the irq_service's<br>
>> calls the functions implemented by the irq_service.c<br>
>> instead.<br>
>><br>
>> The hpd_ack function is replaced by hpd0_ack and hpd1_ack, the<br>
>> required constants are also added.<br>
>><br>
>> The changes were not tested on actual hardware. I am only able<br>
>> to verify that the changes keep the code compileable and do my<br>
>> best to look repeatedly if I am not actually changing any code.<br>
>><br>
>> Signed-off-by: Sebastian Aguilera Novoa <<a href="mailto:saguileran@ime.usp.br" target="_blank" rel="noreferrer">saguileran@ime.usp.br</a>><br>
>> ---<br>
>> .../dc/irq/dce120/irq_service_dce120.c | 29 +--------<br>
>> .../display/dc/irq/dce60/irq_service_dce60.c | 31 +--------<br>
>> .../display/dc/irq/dce80/irq_service_dce80.c | 31 +--------<br>
>> .../display/dc/irq/dcn10/irq_service_dcn10.c | 29 +--------<br>
>> .../display/dc/irq/dcn20/irq_service_dcn20.c | 29 +--------<br>
>> .../dc/irq/dcn201/irq_service_dcn201.c | 29 +--------<br>
>> .../display/dc/irq/dcn21/irq_service_dcn21.c | 29 +--------<br>
>> .../display/dc/irq/dcn30/irq_service_dcn30.c | 30 +--------<br>
>> .../dc/irq/dcn302/irq_service_dcn302.c | 19 +-----<br>
>> .../dc/irq/dcn303/irq_service_dcn303.c | 19 +-----<br>
>> .../display/dc/irq/dcn31/irq_service_dcn31.c | 29 +--------<br>
>> .../dc/irq/dcn314/irq_service_dcn314.c | 29 +--------<br>
>> .../dc/irq/dcn315/irq_service_dcn315.c | 29 +--------<br>
>> .../display/dc/irq/dcn32/irq_service_dcn32.c | 29 +--------<br>
>> .../display/dc/irq/dcn35/irq_service_dcn35.c | 29 +--------<br>
>> .../dc/irq/dcn351/irq_service_dcn351.c | 29 +--------<br>
>> .../display/dc/irq/dcn36/irq_service_dcn36.c | 29 +--------<br>
>> .../dc/irq/dcn401/irq_service_dcn401.c | 29 +--------<br>
>> .../gpu/drm/amd/display/dc/irq/irq_service.c | 64 +++++++++++++++++++<br>
>> .../gpu/drm/amd/display/dc/irq/irq_service.h | 8 +++<br>
>> 20 files changed, 90 insertions(+), 489 deletions(-)<br>
>><br>
>> diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce120/ <br>
>> irq_service_dce120.c b/drivers/gpu/drm/amd/display/dc/irq/dce120/ <br>
>> irq_service_dce120.c<br>
>> index 953f4a4dacad..33ce470e4c88 100644<br>
>> --- a/drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c<br>
>> +++ b/drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c<br>
>> @@ -37,36 +37,9 @@<br>
>> #include "ivsrcid/ivsrcid_vislands30.h"<br>
>> -static bool hpd_ack(<br>
>> - struct irq_service *irq_service,<br>
>> - const struct irq_source_info *info)<br>
>> -{<br>
>> - uint32_t addr = info->status_reg;<br>
>> - uint32_t value = dm_read_reg(irq_service->ctx, addr);<br>
>> - uint32_t current_status =<br>
>> - get_reg_field_value(<br>
>> - value,<br>
>> - HPD0_DC_HPD_INT_STATUS,<br>
>> - DC_HPD_SENSE_DELAYED);<br>
>> -<br>
>> - dal_irq_service_ack_generic(irq_service, info);<br>
>> -<br>
>> - value = dm_read_reg(irq_service->ctx, info->enable_reg);<br>
>> -<br>
>> - set_reg_field_value(<br>
>> - value,<br>
>> - current_status ? 0 : 1,<br>
>> - HPD0_DC_HPD_INT_CONTROL,<br>
>> - DC_HPD_INT_POLARITY);<br>
>> -<br>
>> - dm_write_reg(irq_service->ctx, info->enable_reg, value);<br>
>> -<br>
>> - return true;<br>
>> -}<br>
>> -<br>
>> static struct irq_source_info_funcs hpd_irq_info_funcs = {<br>
>> .set = NULL,<br>
>> - .ack = hpd_ack<br>
>> + .ack = hpd0_ack<br>
>> };<br>
>> static struct irq_source_info_funcs hpd_rx_irq_info_funcs = {<br>
>> diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce60/ <br>
>> irq_service_dce60.c b/drivers/gpu/drm/amd/display/dc/irq/dce60/ <br>
>> irq_service_dce60.c<br>
>> index 2c72074310c7..d777b85e70da 100644<br>
>> --- a/drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c<br>
>> +++ b/drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c<br>
>> @@ -46,36 +46,9 @@<br>
>> #include "dc_types.h"<br>
>> -static bool hpd_ack(<br>
>> - struct irq_service *irq_service,<br>
>> - const struct irq_source_info *info)<br>
>> -{<br>
>> - uint32_t addr = info->status_reg;<br>
>> - uint32_t value = dm_read_reg(irq_service->ctx, addr);<br>
>> - uint32_t current_status =<br>
>> - get_reg_field_value(<br>
>> - value,<br>
>> - DC_HPD1_INT_STATUS,<br>
>> - DC_HPD1_SENSE_DELAYED);<br>
>> -<br>
>> - dal_irq_service_ack_generic(irq_service, info);<br>
>> -<br>
>> - value = dm_read_reg(irq_service->ctx, info->enable_reg);<br>
>> -<br>
>> - set_reg_field_value(<br>
>> - value,<br>
>> - current_status ? 0 : 1,<br>
>> - DC_HPD1_INT_CONTROL,<br>
>> - DC_HPD1_INT_POLARITY);<br>
>> -<br>
>> - dm_write_reg(irq_service->ctx, info->enable_reg, value);<br>
>> -<br>
>> - return true;<br>
>> -}<br>
>> -<br>
>> static struct irq_source_info_funcs hpd_irq_info_funcs = {<br>
>> .set = NULL,<br>
>> - .ack = hpd_ack<br>
>> + .ack = hpd1_ack<br>
>> };<br>
>> static struct irq_source_info_funcs hpd_rx_irq_info_funcs = {<br>
>> @@ -391,5 +364,3 @@ struct irq_service *dal_irq_service_dce60_create(<br>
>> dce60_irq_construct(irq_service, init_data);<br>
>> return irq_service;<br>
>> }<br>
>> -<br>
>> -<br>
>> diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce80/ <br>
>> irq_service_dce80.c b/drivers/gpu/drm/amd/display/dc/irq/dce80/ <br>
>> irq_service_dce80.c<br>
>> index 49317934ef4f..3a9163acb49b 100644<br>
>> --- a/drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c<br>
>> +++ b/drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c<br>
>> @@ -37,36 +37,9 @@<br>
>> #include "dc_types.h"<br>
>> -static bool hpd_ack(<br>
>> - struct irq_service *irq_service,<br>
>> - const struct irq_source_info *info)<br>
>> -{<br>
>> - uint32_t addr = info->status_reg;<br>
>> - uint32_t value = dm_read_reg(irq_service->ctx, addr);<br>
>> - uint32_t current_status =<br>
>> - get_reg_field_value(<br>
>> - value,<br>
>> - DC_HPD1_INT_STATUS,<br>
>> - DC_HPD1_SENSE_DELAYED);<br>
>> -<br>
>> - dal_irq_service_ack_generic(irq_service, info);<br>
>> -<br>
>> - value = dm_read_reg(irq_service->ctx, info->enable_reg);<br>
>> -<br>
>> - set_reg_field_value(<br>
>> - value,<br>
>> - current_status ? 0 : 1,<br>
>> - DC_HPD1_INT_CONTROL,<br>
>> - DC_HPD1_INT_POLARITY);<br>
>> -<br>
>> - dm_write_reg(irq_service->ctx, info->enable_reg, value);<br>
>> -<br>
>> - return true;<br>
>> -}<br>
>> -<br>
>> static struct irq_source_info_funcs hpd_irq_info_funcs = {<br>
>> .set = NULL,<br>
>> - .ack = hpd_ack<br>
>> + .ack = hpd1_ack<br>
>> };<br>
>> static struct irq_source_info_funcs hpd_rx_irq_info_funcs = {<br>
>> @@ -303,5 +276,3 @@ struct irq_service *dal_irq_service_dce80_create(<br>
>> dce80_irq_construct(irq_service, init_data);<br>
>> return irq_service;<br>
>> }<br>
>> -<br>
>> -<br>
>> diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn10/ <br>
>> irq_service_dcn10.c b/drivers/gpu/drm/amd/display/dc/irq/dcn10/ <br>
>> irq_service_dcn10.c<br>
>> index 9ca28565a9d1..4ce9edd16344 100644<br>
>> --- a/drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c<br>
>> +++ b/drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c<br>
>> @@ -129,36 +129,9 @@ static enum dc_irq_source <br>
>> to_dal_irq_source_dcn10(struct irq_service *irq_servic<br>
>> }<br>
>> }<br>
>> -static bool hpd_ack(<br>
>> - struct irq_service *irq_service,<br>
>> - const struct irq_source_info *info)<br>
>> -{<br>
>> - uint32_t addr = info->status_reg;<br>
>> - uint32_t value = dm_read_reg(irq_service->ctx, addr);<br>
>> - uint32_t current_status =<br>
>> - get_reg_field_value(<br>
>> - value,<br>
>> - HPD0_DC_HPD_INT_STATUS,<br>
>> - DC_HPD_SENSE_DELAYED);<br>
>> -<br>
>> - dal_irq_service_ack_generic(irq_service, info);<br>
>> -<br>
>> - value = dm_read_reg(irq_service->ctx, info->enable_reg);<br>
>> -<br>
>> - set_reg_field_value(<br>
>> - value,<br>
>> - current_status ? 0 : 1,<br>
>> - HPD0_DC_HPD_INT_CONTROL,<br>
>> - DC_HPD_INT_POLARITY);<br>
>> -<br>
>> - dm_write_reg(irq_service->ctx, info->enable_reg, value);<br>
>> -<br>
>> - return true;<br>
>> -}<br>
>> -<br>
>> static struct irq_source_info_funcs hpd_irq_info_funcs = {<br>
>> .set = NULL,<br>
>> - .ack = hpd_ack<br>
>> + .ack = hpd0_ack<br>
>> };<br>
>> static struct irq_source_info_funcs hpd_rx_irq_info_funcs = {<br>
>> diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn20/ <br>
>> irq_service_dcn20.c b/drivers/gpu/drm/amd/display/dc/irq/dcn20/ <br>
>> irq_service_dcn20.c<br>
>> index 916f0c974637..5847af0e66cb 100644<br>
>> --- a/drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c<br>
>> +++ b/drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c<br>
>> @@ -130,36 +130,9 @@ static enum dc_irq_source to_dal_irq_source_dcn20(<br>
>> }<br>
>> }<br>
>> -static bool hpd_ack(<br>
>> - struct irq_service *irq_service,<br>
>> - const struct irq_source_info *info)<br>
>> -{<br>
>> - uint32_t addr = info->status_reg;<br>
>> - uint32_t value = dm_read_reg(irq_service->ctx, addr);<br>
>> - uint32_t current_status =<br>
>> - get_reg_field_value(<br>
>> - value,<br>
>> - HPD0_DC_HPD_INT_STATUS,<br>
>> - DC_HPD_SENSE_DELAYED);<br>
>> -<br>
>> - dal_irq_service_ack_generic(irq_service, info);<br>
>> -<br>
>> - value = dm_read_reg(irq_service->ctx, info->enable_reg);<br>
>> -<br>
>> - set_reg_field_value(<br>
>> - value,<br>
>> - current_status ? 0 : 1,<br>
>> - HPD0_DC_HPD_INT_CONTROL,<br>
>> - DC_HPD_INT_POLARITY);<br>
>> -<br>
>> - dm_write_reg(irq_service->ctx, info->enable_reg, value);<br>
>> -<br>
>> - return true;<br>
>> -}<br>
>> -<br>
>> static struct irq_source_info_funcs hpd_irq_info_funcs = {<br>
>> .set = NULL,<br>
>> - .ack = hpd_ack<br>
>> + .ack = hpd0_ack<br>
>> };<br>
>> static struct irq_source_info_funcs hpd_rx_irq_info_funcs = {<br>
>> diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn201/ <br>
>> irq_service_dcn201.c b/drivers/gpu/drm/amd/display/dc/irq/dcn201/ <br>
>> irq_service_dcn201.c<br>
>> index 1d61d475d36f..6417011d2246 100644<br>
>> --- a/drivers/gpu/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c<br>
>> +++ b/drivers/gpu/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c<br>
>> @@ -80,36 +80,9 @@ static enum dc_irq_source to_dal_irq_source_dcn201(<br>
>> }<br>
>> }<br>
>> -static bool hpd_ack(<br>
>> - struct irq_service *irq_service,<br>
>> - const struct irq_source_info *info)<br>
>> -{<br>
>> - uint32_t addr = info->status_reg;<br>
>> - uint32_t value = dm_read_reg(irq_service->ctx, addr);<br>
>> - uint32_t current_status =<br>
>> - get_reg_field_value(<br>
>> - value,<br>
>> - HPD0_DC_HPD_INT_STATUS,<br>
>> - DC_HPD_SENSE_DELAYED);<br>
>> -<br>
>> - dal_irq_service_ack_generic(irq_service, info);<br>
>> -<br>
>> - value = dm_read_reg(irq_service->ctx, info->enable_reg);<br>
>> -<br>
>> - set_reg_field_value(<br>
>> - value,<br>
>> - current_status ? 0 : 1,<br>
>> - HPD0_DC_HPD_INT_CONTROL,<br>
>> - DC_HPD_INT_POLARITY);<br>
>> -<br>
>> - dm_write_reg(irq_service->ctx, info->enable_reg, value);<br>
>> -<br>
>> - return true;<br>
>> -}<br>
>> -<br>
>> static struct irq_source_info_funcs hpd_irq_info_funcs = {<br>
>> .set = NULL,<br>
>> - .ack = hpd_ack<br>
>> + .ack = hpd0_ack<br>
>> };<br>
>> static struct irq_source_info_funcs hpd_rx_irq_info_funcs = {<br>
>> diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn21/ <br>
>> irq_service_dcn21.c b/drivers/gpu/drm/amd/display/dc/irq/dcn21/ <br>
>> irq_service_dcn21.c<br>
>> index 42cdfe6c3538..71d2f065140b 100644<br>
>> --- a/drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c<br>
>> +++ b/drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c<br>
>> @@ -132,36 +132,9 @@ static enum dc_irq_source <br>
>> to_dal_irq_source_dcn21(struct irq_service *irq_servic<br>
>> return DC_IRQ_SOURCE_INVALID;<br>
>> }<br>
>> -static bool hpd_ack(<br>
>> - struct irq_service *irq_service,<br>
>> - const struct irq_source_info *info)<br>
>> -{<br>
>> - uint32_t addr = info->status_reg;<br>
>> - uint32_t value = dm_read_reg(irq_service->ctx, addr);<br>
>> - uint32_t current_status =<br>
>> - get_reg_field_value(<br>
>> - value,<br>
>> - HPD0_DC_HPD_INT_STATUS,<br>
>> - DC_HPD_SENSE_DELAYED);<br>
>> -<br>
>> - dal_irq_service_ack_generic(irq_service, info);<br>
>> -<br>
>> - value = dm_read_reg(irq_service->ctx, info->enable_reg);<br>
>> -<br>
>> - set_reg_field_value(<br>
>> - value,<br>
>> - current_status ? 0 : 1,<br>
>> - HPD0_DC_HPD_INT_CONTROL,<br>
>> - DC_HPD_INT_POLARITY);<br>
>> -<br>
>> - dm_write_reg(irq_service->ctx, info->enable_reg, value);<br>
>> -<br>
>> - return true;<br>
>> -}<br>
>> -<br>
>> static struct irq_source_info_funcs hpd_irq_info_funcs = {<br>
>> .set = NULL,<br>
>> - .ack = hpd_ack<br>
>> + .ack = hpd0_ack<br>
>> };<br>
>> static struct irq_source_info_funcs hpd_rx_irq_info_funcs = {<br>
>> diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn30/ <br>
>> irq_service_dcn30.c b/drivers/gpu/drm/amd/display/dc/irq/dcn30/ <br>
>> irq_service_dcn30.c<br>
>> index a443a8abb1ea..2a4080bdcf6b 100644<br>
>> --- a/drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c<br>
>> +++ b/drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c<br>
>> @@ -139,36 +139,9 @@ static enum dc_irq_source to_dal_irq_source_dcn30(<br>
>> }<br>
>> }<br>
>> -static bool hpd_ack(<br>
>> - struct irq_service *irq_service,<br>
>> - const struct irq_source_info *info)<br>
>> -{<br>
>> - uint32_t addr = info->status_reg;<br>
>> - uint32_t value = dm_read_reg(irq_service->ctx, addr);<br>
>> - uint32_t current_status =<br>
>> - get_reg_field_value(<br>
>> - value,<br>
>> - HPD0_DC_HPD_INT_STATUS,<br>
>> - DC_HPD_SENSE_DELAYED);<br>
>> -<br>
>> - dal_irq_service_ack_generic(irq_service, info);<br>
>> -<br>
>> - value = dm_read_reg(irq_service->ctx, info->enable_reg);<br>
>> -<br>
>> - set_reg_field_value(<br>
>> - value,<br>
>> - current_status ? 0 : 1,<br>
>> - HPD0_DC_HPD_INT_CONTROL,<br>
>> - DC_HPD_INT_POLARITY);<br>
>> -<br>
>> - dm_write_reg(irq_service->ctx, info->enable_reg, value);<br>
>> -<br>
>> - return true;<br>
>> -}<br>
>> -<br>
>> static struct irq_source_info_funcs hpd_irq_info_funcs = {<br>
>> .set = NULL,<br>
>> - .ack = hpd_ack<br>
>> + .ack = hpd0_ack<br>
>> };<br>
>> static struct irq_source_info_funcs hpd_rx_irq_info_funcs = {<br>
>> @@ -447,4 +420,3 @@ struct irq_service *dal_irq_service_dcn30_create(<br>
>> dcn30_irq_construct(irq_service, init_data);<br>
>> return irq_service;<br>
>> }<br>
>> -<br>
>> diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn302/ <br>
>> irq_service_dcn302.c b/drivers/gpu/drm/amd/display/dc/irq/dcn302/ <br>
>> irq_service_dcn302.c<br>
>> index 8ffc7e2c681a..624f1ac309f8 100644<br>
>> --- a/drivers/gpu/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c<br>
>> +++ b/drivers/gpu/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c<br>
>> @@ -126,26 +126,9 @@ static enum dc_irq_source <br>
>> to_dal_irq_source_dcn302(struct irq_service *irq_servi<br>
>> }<br>
>> }<br>
>> -static bool hpd_ack(struct irq_service *irq_service, const struct <br>
>> irq_source_info *info)<br>
>> -{<br>
>> - uint32_t addr = info->status_reg;<br>
>> - uint32_t value = dm_read_reg(irq_service->ctx, addr);<br>
>> - uint32_t current_status = get_reg_field_value(value, <br>
>> HPD0_DC_HPD_INT_STATUS, DC_HPD_SENSE_DELAYED);<br>
>> -<br>
>> - dal_irq_service_ack_generic(irq_service, info);<br>
>> -<br>
>> - value = dm_read_reg(irq_service->ctx, info->enable_reg);<br>
>> -<br>
>> - set_reg_field_value(value, current_status ? 0 : 1, <br>
>> HPD0_DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY);<br>
>> -<br>
>> - dm_write_reg(irq_service->ctx, info->enable_reg, value);<br>
>> -<br>
>> - return true;<br>
>> -}<br>
>> -<br>
>> static struct irq_source_info_funcs hpd_irq_info_funcs = {<br>
>> .set = NULL,<br>
>> - .ack = hpd_ack<br>
>> + .ack = hpd0_ack<br>
>> };<br>
>> static struct irq_source_info_funcs hpd_rx_irq_info_funcs = {<br>
>> diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn303/ <br>
>> irq_service_dcn303.c b/drivers/gpu/drm/amd/display/dc/irq/dcn303/ <br>
>> irq_service_dcn303.c<br>
>> index 262bb8b74b15..137caffae916 100644<br>
>> --- a/drivers/gpu/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c<br>
>> +++ b/drivers/gpu/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c<br>
>> @@ -77,26 +77,9 @@ static enum dc_irq_source <br>
>> to_dal_irq_source_dcn303(struct irq_service *irq_servi<br>
>> }<br>
>> }<br>
>> -static bool hpd_ack(struct irq_service *irq_service, const struct <br>
>> irq_source_info *info)<br>
>> -{<br>
>> - uint32_t addr = info->status_reg;<br>
>> - uint32_t value = dm_read_reg(irq_service->ctx, addr);<br>
>> - uint32_t current_status = get_reg_field_value(value, <br>
>> HPD0_DC_HPD_INT_STATUS, DC_HPD_SENSE_DELAYED);<br>
>> -<br>
>> - dal_irq_service_ack_generic(irq_service, info);<br>
>> -<br>
>> - value = dm_read_reg(irq_service->ctx, info->enable_reg);<br>
>> -<br>
>> - set_reg_field_value(value, current_status ? 0 : 1, <br>
>> HPD0_DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY);<br>
>> -<br>
>> - dm_write_reg(irq_service->ctx, info->enable_reg, value);<br>
>> -<br>
>> - return true;<br>
>> -}<br>
>> -<br>
>> static struct irq_source_info_funcs hpd_irq_info_funcs = {<br>
>> .set = NULL,<br>
>> - .ack = hpd_ack<br>
>> + .ack = hpd0_ack<br>
>> };<br>
>> static struct irq_source_info_funcs hpd_rx_irq_info_funcs = {<br>
>> diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn31/ <br>
>> irq_service_dcn31.c b/drivers/gpu/drm/amd/display/dc/irq/dcn31/ <br>
>> irq_service_dcn31.c<br>
>> index 53e78ae7eecf..921cb167d920 100644<br>
>> --- a/drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c<br>
>> +++ b/drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c<br>
>> @@ -128,36 +128,9 @@ static enum dc_irq_source <br>
>> to_dal_irq_source_dcn31(struct irq_service *irq_servic<br>
>> }<br>
>> }<br>
>> -static bool hpd_ack(<br>
>> - struct irq_service *irq_service,<br>
>> - const struct irq_source_info *info)<br>
>> -{<br>
>> - uint32_t addr = info->status_reg;<br>
>> - uint32_t value = dm_read_reg(irq_service->ctx, addr);<br>
>> - uint32_t current_status =<br>
>> - get_reg_field_value(<br>
>> - value,<br>
>> - HPD0_DC_HPD_INT_STATUS,<br>
>> - DC_HPD_SENSE_DELAYED);<br>
>> -<br>
>> - dal_irq_service_ack_generic(irq_service, info);<br>
>> -<br>
>> - value = dm_read_reg(irq_service->ctx, info->enable_reg);<br>
>> -<br>
>> - set_reg_field_value(<br>
>> - value,<br>
>> - current_status ? 0 : 1,<br>
>> - HPD0_DC_HPD_INT_CONTROL,<br>
>> - DC_HPD_INT_POLARITY);<br>
>> -<br>
>> - dm_write_reg(irq_service->ctx, info->enable_reg, value);<br>
>> -<br>
>> - return true;<br>
>> -}<br>
>> -<br>
>> static struct irq_source_info_funcs hpd_irq_info_funcs = {<br>
>> .set = NULL,<br>
>> - .ack = hpd_ack<br>
>> + .ack = hpd0_ack<br>
>> };<br>
>> static struct irq_source_info_funcs hpd_rx_irq_info_funcs = {<br>
>> diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn314/ <br>
>> irq_service_dcn314.c b/drivers/gpu/drm/amd/display/dc/irq/dcn314/ <br>
>> irq_service_dcn314.c<br>
>> index e0563e880432..0118fd6e5db0 100644<br>
>> --- a/drivers/gpu/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c<br>
>> +++ b/drivers/gpu/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c<br>
>> @@ -130,36 +130,9 @@ static enum dc_irq_source <br>
>> to_dal_irq_source_dcn314(struct irq_service *irq_servi<br>
>> }<br>
>> }<br>
>> -static bool hpd_ack(<br>
>> - struct irq_service *irq_service,<br>
>> - const struct irq_source_info *info)<br>
>> -{<br>
>> - uint32_t addr = info->status_reg;<br>
>> - uint32_t value = dm_read_reg(irq_service->ctx, addr);<br>
>> - uint32_t current_status =<br>
>> - get_reg_field_value(<br>
>> - value,<br>
>> - HPD0_DC_HPD_INT_STATUS,<br>
>> - DC_HPD_SENSE_DELAYED);<br>
>> -<br>
>> - dal_irq_service_ack_generic(irq_service, info);<br>
>> -<br>
>> - value = dm_read_reg(irq_service->ctx, info->enable_reg);<br>
>> -<br>
>> - set_reg_field_value(<br>
>> - value,<br>
>> - current_status ? 0 : 1,<br>
>> - HPD0_DC_HPD_INT_CONTROL,<br>
>> - DC_HPD_INT_POLARITY);<br>
>> -<br>
>> - dm_write_reg(irq_service->ctx, info->enable_reg, value);<br>
>> -<br>
>> - return true;<br>
>> -}<br>
>> -<br>
>> static struct irq_source_info_funcs hpd_irq_info_funcs = {<br>
>> .set = NULL,<br>
>> - .ack = hpd_ack<br>
>> + .ack = hpd0_ack<br>
>> };<br>
>> static struct irq_source_info_funcs hpd_rx_irq_info_funcs = {<br>
>> diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn315/ <br>
>> irq_service_dcn315.c b/drivers/gpu/drm/amd/display/dc/irq/dcn315/ <br>
>> irq_service_dcn315.c<br>
>> index 2ef22299101a..adebfc888618 100644<br>
>> --- a/drivers/gpu/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c<br>
>> +++ b/drivers/gpu/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c<br>
>> @@ -135,36 +135,9 @@ static enum dc_irq_source to_dal_irq_source_dcn315(<br>
>> }<br>
>> }<br>
>> -static bool hpd_ack(<br>
>> - struct irq_service *irq_service,<br>
>> - const struct irq_source_info *info)<br>
>> -{<br>
>> - uint32_t addr = info->status_reg;<br>
>> - uint32_t value = dm_read_reg(irq_service->ctx, addr);<br>
>> - uint32_t current_status =<br>
>> - get_reg_field_value(<br>
>> - value,<br>
>> - HPD0_DC_HPD_INT_STATUS,<br>
>> - DC_HPD_SENSE_DELAYED);<br>
>> -<br>
>> - dal_irq_service_ack_generic(irq_service, info);<br>
>> -<br>
>> - value = dm_read_reg(irq_service->ctx, info->enable_reg);<br>
>> -<br>
>> - set_reg_field_value(<br>
>> - value,<br>
>> - current_status ? 0 : 1,<br>
>> - HPD0_DC_HPD_INT_CONTROL,<br>
>> - DC_HPD_INT_POLARITY);<br>
>> -<br>
>> - dm_write_reg(irq_service->ctx, info->enable_reg, value);<br>
>> -<br>
>> - return true;<br>
>> -}<br>
>> -<br>
>> static struct irq_source_info_funcs hpd_irq_info_funcs = {<br>
>> .set = NULL,<br>
>> - .ack = hpd_ack<br>
>> + .ack = hpd0_ack<br>
>> };<br>
>> static struct irq_source_info_funcs hpd_rx_irq_info_funcs = {<br>
>> diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn32/ <br>
>> irq_service_dcn32.c b/drivers/gpu/drm/amd/display/dc/irq/dcn32/ <br>
>> irq_service_dcn32.c<br>
>> index f839afacd5a5..e9e315c75d76 100644<br>
>> --- a/drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c<br>
>> +++ b/drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c<br>
>> @@ -129,36 +129,9 @@ static enum dc_irq_source to_dal_irq_source_dcn32(<br>
>> }<br>
>> }<br>
>> -static bool hpd_ack(<br>
>> - struct irq_service *irq_service,<br>
>> - const struct irq_source_info *info)<br>
>> -{<br>
>> - uint32_t addr = info->status_reg;<br>
>> - uint32_t value = dm_read_reg(irq_service->ctx, addr);<br>
>> - uint32_t current_status =<br>
>> - get_reg_field_value(<br>
>> - value,<br>
>> - HPD0_DC_HPD_INT_STATUS,<br>
>> - DC_HPD_SENSE_DELAYED);<br>
>> -<br>
>> - dal_irq_service_ack_generic(irq_service, info);<br>
>> -<br>
>> - value = dm_read_reg(irq_service->ctx, info->enable_reg);<br>
>> -<br>
>> - set_reg_field_value(<br>
>> - value,<br>
>> - current_status ? 0 : 1,<br>
>> - HPD0_DC_HPD_INT_CONTROL,<br>
>> - DC_HPD_INT_POLARITY);<br>
>> -<br>
>> - dm_write_reg(irq_service->ctx, info->enable_reg, value);<br>
>> -<br>
>> - return true;<br>
>> -}<br>
>> -<br>
>> static struct irq_source_info_funcs hpd_irq_info_funcs = {<br>
>> .set = NULL,<br>
>> - .ack = hpd_ack<br>
>> + .ack = hpd0_ack<br>
>> };<br>
>> static struct irq_source_info_funcs hpd_rx_irq_info_funcs = {<br>
>> diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn35/ <br>
>> irq_service_dcn35.c b/drivers/gpu/drm/amd/display/dc/irq/dcn35/ <br>
>> irq_service_dcn35.c<br>
>> index ea8c271171bc..79e5e8c137ca 100644<br>
>> --- a/drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c<br>
>> +++ b/drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c<br>
>> @@ -127,36 +127,9 @@ static enum dc_irq_source to_dal_irq_source_dcn35(<br>
>> }<br>
>> }<br>
>> -static bool hpd_ack(<br>
>> - struct irq_service *irq_service,<br>
>> - const struct irq_source_info *info)<br>
>> -{<br>
>> - uint32_t addr = info->status_reg;<br>
>> - uint32_t value = dm_read_reg(irq_service->ctx, addr);<br>
>> - uint32_t current_status =<br>
>> - get_reg_field_value(<br>
>> - value,<br>
>> - HPD0_DC_HPD_INT_STATUS,<br>
>> - DC_HPD_SENSE_DELAYED);<br>
>> -<br>
>> - dal_irq_service_ack_generic(irq_service, info);<br>
>> -<br>
>> - value = dm_read_reg(irq_service->ctx, info->enable_reg);<br>
>> -<br>
>> - set_reg_field_value(<br>
>> - value,<br>
>> - current_status ? 0 : 1,<br>
>> - HPD0_DC_HPD_INT_CONTROL,<br>
>> - DC_HPD_INT_POLARITY);<br>
>> -<br>
>> - dm_write_reg(irq_service->ctx, info->enable_reg, value);<br>
>> -<br>
>> - return true;<br>
>> -}<br>
>> -<br>
>> static struct irq_source_info_funcs hpd_irq_info_funcs = {<br>
>> .set = NULL,<br>
>> - .ack = hpd_ack<br>
>> + .ack = hpd0_ack<br>
>> };<br>
>> static struct irq_source_info_funcs hpd_rx_irq_info_funcs = {<br>
>> diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn351/ <br>
>> irq_service_dcn351.c b/drivers/gpu/drm/amd/display/dc/irq/dcn351/ <br>
>> irq_service_dcn351.c<br>
>> index 7ec8e0de2f01..163b8ee9ebf7 100644<br>
>> --- a/drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c<br>
>> +++ b/drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c<br>
>> @@ -106,36 +106,9 @@ static enum dc_irq_source to_dal_irq_source_dcn351(<br>
>> }<br>
>> }<br>
>> -static bool hpd_ack(<br>
>> - struct irq_service *irq_service,<br>
>> - const struct irq_source_info *info)<br>
>> -{<br>
>> - uint32_t addr = info->status_reg;<br>
>> - uint32_t value = dm_read_reg(irq_service->ctx, addr);<br>
>> - uint32_t current_status =<br>
>> - get_reg_field_value(<br>
>> - value,<br>
>> - HPD0_DC_HPD_INT_STATUS,<br>
>> - DC_HPD_SENSE_DELAYED);<br>
>> -<br>
>> - dal_irq_service_ack_generic(irq_service, info);<br>
>> -<br>
>> - value = dm_read_reg(irq_service->ctx, info->enable_reg);<br>
>> -<br>
>> - set_reg_field_value(<br>
>> - value,<br>
>> - current_status ? 0 : 1,<br>
>> - HPD0_DC_HPD_INT_CONTROL,<br>
>> - DC_HPD_INT_POLARITY);<br>
>> -<br>
>> - dm_write_reg(irq_service->ctx, info->enable_reg, value);<br>
>> -<br>
>> - return true;<br>
>> -}<br>
>> -<br>
>> static struct irq_source_info_funcs hpd_irq_info_funcs = {<br>
>> .set = NULL,<br>
>> - .ack = hpd_ack<br>
>> + .ack = hpd0_ack<br>
>> };<br>
>> static struct irq_source_info_funcs hpd_rx_irq_info_funcs = {<br>
>> diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn36/ <br>
>> irq_service_dcn36.c b/drivers/gpu/drm/amd/display/dc/irq/dcn36/ <br>
>> irq_service_dcn36.c<br>
>> index ea958628f8b8..f716ab0fd30e 100644<br>
>> --- a/drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c<br>
>> +++ b/drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c<br>
>> @@ -105,36 +105,9 @@ static enum dc_irq_source to_dal_irq_source_dcn36(<br>
>> }<br>
>> }<br>
>> -static bool hpd_ack(<br>
>> - struct irq_service *irq_service,<br>
>> - const struct irq_source_info *info)<br>
>> -{<br>
>> - uint32_t addr = info->status_reg;<br>
>> - uint32_t value = dm_read_reg(irq_service->ctx, addr);<br>
>> - uint32_t current_status =<br>
>> - get_reg_field_value(<br>
>> - value,<br>
>> - HPD0_DC_HPD_INT_STATUS,<br>
>> - DC_HPD_SENSE_DELAYED);<br>
>> -<br>
>> - dal_irq_service_ack_generic(irq_service, info);<br>
>> -<br>
>> - value = dm_read_reg(irq_service->ctx, info->enable_reg);<br>
>> -<br>
>> - set_reg_field_value(<br>
>> - value,<br>
>> - current_status ? 0 : 1,<br>
>> - HPD0_DC_HPD_INT_CONTROL,<br>
>> - DC_HPD_INT_POLARITY);<br>
>> -<br>
>> - dm_write_reg(irq_service->ctx, info->enable_reg, value);<br>
>> -<br>
>> - return true;<br>
>> -}<br>
>> -<br>
>> static struct irq_source_info_funcs hpd_irq_info_funcs = {<br>
>> .set = NULL,<br>
>> - .ack = hpd_ack<br>
>> + .ack = hpd0_ack<br>
>> };<br>
>> static struct irq_source_info_funcs hpd_rx_irq_info_funcs = {<br>
>> diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn401/ <br>
>> irq_service_dcn401.c b/drivers/gpu/drm/amd/display/dc/irq/dcn401/ <br>
>> irq_service_dcn401.c<br>
>> index 8499e505cf3e..fd9bb1950c20 100644<br>
>> --- a/drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c<br>
>> +++ b/drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c<br>
>> @@ -109,36 +109,9 @@ static enum dc_irq_source to_dal_irq_source_dcn401(<br>
>> }<br>
>> }<br>
>> -static bool hpd_ack(<br>
>> - struct irq_service *irq_service,<br>
>> - const struct irq_source_info *info)<br>
>> -{<br>
>> - uint32_t addr = info->status_reg;<br>
>> - uint32_t value = dm_read_reg(irq_service->ctx, addr);<br>
>> - uint32_t current_status =<br>
>> - get_reg_field_value(<br>
>> - value,<br>
>> - HPD0_DC_HPD_INT_STATUS,<br>
>> - DC_HPD_SENSE_DELAYED);<br>
>> -<br>
>> - dal_irq_service_ack_generic(irq_service, info);<br>
>> -<br>
>> - value = dm_read_reg(irq_service->ctx, info->enable_reg);<br>
>> -<br>
>> - set_reg_field_value(<br>
>> - value,<br>
>> - current_status ? 0 : 1,<br>
>> - HPD0_DC_HPD_INT_CONTROL,<br>
>> - DC_HPD_INT_POLARITY);<br>
>> -<br>
>> - dm_write_reg(irq_service->ctx, info->enable_reg, value);<br>
>> -<br>
>> - return true;<br>
>> -}<br>
>> -<br>
>> static struct irq_source_info_funcs hpd_irq_info_funcs = {<br>
>> .set = NULL,<br>
>> - .ack = hpd_ack<br>
>> + .ack = hpd0_ack<br>
>> };<br>
>> static struct irq_source_info_funcs hpd_rx_irq_info_funcs = {<br>
>> diff --git a/drivers/gpu/drm/amd/display/dc/irq/irq_service.c b/ <br>
>> drivers/gpu/drm/amd/display/dc/irq/irq_service.c<br>
>> index eca3d7ee7e4e..b595a11c5eaf 100644<br>
>> --- a/drivers/gpu/drm/amd/display/dc/irq/irq_service.c<br>
>> +++ b/drivers/gpu/drm/amd/display/dc/irq/irq_service.c<br>
>> @@ -41,6 +41,16 @@<br>
>> #include "reg_helper.h"<br>
>> #include "irq_service.h"<br>
>> +//HPD0_DC_HPD_INT_STATUS<br>
>> +#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK <br>
>> 0x00000010L<br>
>> +#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK <br>
>> 0x00000100L<br>
>> +#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT 0x4<br>
>> +#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT 0x8<br>
>> +//HPD1_DC_HPD_INT_STATUS<br>
>> +#define DC_HPD1_INT_STATUS__DC_HPD1_SENSE_DELAYED_MASK 0x10<br>
>> +#define DC_HPD1_INT_STATUS__DC_HPD1_SENSE_DELAYED__SHIFT 0x4<br>
>> +#define DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK 0x100<br>
>> +#define DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY__SHIFT 0x8<br>
>> #define CTX \<br>
>> @@ -177,3 +187,57 @@ enum dc_irq_source dal_irq_service_to_irq_source(<br>
>> src_id,<br>
>> ext_id);<br>
>> }<br>
>> +<br>
>> +bool hpd0_ack(<br>
>> + struct irq_service *irq_service,<br>
>> + const struct irq_source_info *info)<br>
>> +{<br>
>> + uint32_t addr = info->status_reg;<br>
>> + uint32_t value = dm_read_reg(irq_service->ctx, addr);<br>
>> + uint32_t current_status =<br>
>> + get_reg_field_value(<br>
>> + value,<br>
>> + HPD0_DC_HPD_INT_STATUS,<br>
>> + DC_HPD_SENSE_DELAYED);<br>
>> +<br>
>> + dal_irq_service_ack_generic(irq_service, info);<br>
>> +<br>
>> + value = dm_read_reg(irq_service->ctx, info->enable_reg);<br>
>> +<br>
>> + set_reg_field_value(<br>
>> + value,<br>
>> + current_status ? 0 : 1,<br>
>> + HPD0_DC_HPD_INT_CONTROL,<br>
>> + DC_HPD_INT_POLARITY);<br>
>> +<br>
>> + dm_write_reg(irq_service->ctx, info->enable_reg, value);<br>
>> +<br>
>> + return true;<br>
>> +}<br>
>> +<br>
>> +bool hpd1_ack(<br>
>> + struct irq_service *irq_service,<br>
>> + const struct irq_source_info *info)<br>
>> +{<br>
>> + uint32_t addr = info->status_reg;<br>
>> + uint32_t value = dm_read_reg(irq_service->ctx, addr);<br>
>> + uint32_t current_status =<br>
>> + get_reg_field_value(<br>
>> + value,<br>
>> + DC_HPD1_INT_STATUS,<br>
>> + DC_HPD1_SENSE_DELAYED);<br>
>> +<br>
>> + dal_irq_service_ack_generic(irq_service, info);<br>
>> +<br>
>> + value = dm_read_reg(irq_service->ctx, info->enable_reg);<br>
>> +<br>
>> + set_reg_field_value(<br>
>> + value,<br>
>> + current_status ? 0 : 1,<br>
>> + DC_HPD1_INT_CONTROL,<br>
>> + DC_HPD1_INT_POLARITY);<br>
>> +<br>
>> + dm_write_reg(irq_service->ctx, info->enable_reg, value);<br>
>> +<br>
>> + return true;<br>
>> +}<br>
>> diff --git a/drivers/gpu/drm/amd/display/dc/irq/irq_service.h b/ <br>
>> drivers/gpu/drm/amd/display/dc/irq/irq_service.h<br>
>> index b178f85944cd..bbcef3d2fe33 100644<br>
>> --- a/drivers/gpu/drm/amd/display/dc/irq/irq_service.h<br>
>> +++ b/drivers/gpu/drm/amd/display/dc/irq/irq_service.h<br>
>> @@ -82,4 +82,12 @@ void dal_irq_service_set_generic(<br>
>> const struct irq_source_info *info,<br>
>> bool enable);<br>
>> +bool hpd0_ack(<br>
>> + struct irq_service *irq_service,<br>
>> + const struct irq_source_info *info);<br>
>> +<br>
>> +bool hpd1_ack(<br>
>> + struct irq_service *irq_service,<br>
>> + const struct irq_source_info *info);<br>
>> +<br>
>> #endif<br>
> <br>
<br>
</blockquote></div>