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Reviewed-by: Alex Deucher <alexander.deucher@amd.com></div>
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<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> Wu, David <David.Wu3@amd.com><br>
<b>Sent:</b> Tuesday, May 13, 2025 6:12 PM<br>
<b>To:</b> amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org>; Koenig, Christian <Christian.Koenig@amd.com><br>
<b>Cc:</b> Deucher, Alexander <Alexander.Deucher@amd.com>; Liu, Leo <Leo.Liu@amd.com>; Jiang, Sonny <Sonny.Jiang@amd.com>; Dong, Ruijing <Ruijing.Dong@amd.com>; stable@vger.kernel.org <stable@vger.kernel.org>; Limonciello, Mario <Mario.Limonciello@amd.com><br>
<b>Subject:</b> [PATCH v4] drm/amdgpu: read back register after written for VCN v4.0.5</font>
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<div class="PlainText">V4: add read-back for non-DPG case. This is for protection<br>
purpose as it is not used for producton.<br>
<br>
On VCN v4.0.5 there is a race condition where the WPTR is not<br>
updated after starting from idle when doorbell is used. Adding<br>
register read-back after written at function end is to ensure<br>
all register writes are done before they can be used.<br>
<br>
Closes: <a href="https://gitlab.freedesktop.org/mesa/mesa/-/issues/12528">https://gitlab.freedesktop.org/mesa/mesa/-/issues/12528</a><br>
Cc: stable@vger.kernel.org<br>
<br>
Signed-off-by: David (Ming Qiang) Wu <David.Wu3@amd.com><br>
Reviewed-by: Mario Limonciello <mario.limonciello@amd.com><br>
Tested-by: Mario Limonciello <mario.limonciello@amd.com><br>
---<br>
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 8 ++++++++<br>
1 file changed, 8 insertions(+)<br>
<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c<br>
index ed00d35039c1..a09f9a2dd471 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c<br>
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c<br>
@@ -1034,6 +1034,10 @@ static int vcn_v4_0_5_start_dpg_mode(struct amdgpu_vcn_inst *vinst,<br>
ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT |<br>
VCN_RB1_DB_CTRL__EN_MASK);<br>
<br>
+ /* Keeping one read-back to ensure all register writes are done, otherwise<br>
+ * it may introduce race conditions */<br>
+ RREG32_SOC15(VCN, inst_idx, regVCN_RB1_DB_CTRL);<br>
+<br>
return 0;<br>
}<br>
<br>
@@ -1216,6 +1220,10 @@ static int vcn_v4_0_5_start(struct amdgpu_vcn_inst *vinst)<br>
WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp);<br>
fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF);<br>
<br>
+ /* Keeping one read-back to ensure all register writes are done, otherwise<br>
+ * it may introduce race conditions */<br>
+ RREG32_SOC15(VCN, i, regVCN_RB_ENABLE);<br>
+<br>
return 0;<br>
}<br>
<br>
-- <br>
2.34.1<br>
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