<!DOCTYPE html><html><head> <meta http-equiv="Content-Type" content="text/html; charset=utf-8"> </head> <body> hmm... I knew that - but I would rather add that in case jpeg_v1_0_start() might change. A little conservative ... Thanks, David <div class="moz-cite-prefix">On 5/14/2025 1:33 PM, Dong, Ruijing wrote: </div> <blockquote type="cite" cite="mid:SJ1PR12MB61949015407F2749BDD2A8499591A@SJ1PR12MB6194.namprd12.prod.outlook.com"> <pre wrap="" class="moz-quote-pre">[AMD Official Use Only - AMD Internal Distribution Only] This patch is not needed as it has the read-back in jpeg_v1_0_start(); Thanks, Ruijing -----Original Message----- From: Wu, David <a class="moz-txt-link-rfc2396E" href="mailto:David.Wu3@amd.com"><David.Wu3@amd.com></a> Sent: Wednesday, May 14, 2025 1:23 PM To: <a class="moz-txt-link-abbreviated" href="mailto:amd-gfx@lists.freedesktop.org">amd-gfx@lists.freedesktop.org</a>; Deucher, Alexander <a class="moz-txt-link-rfc2396E" href="mailto:Alexander.Deucher@amd.com"><Alexander.Deucher@amd.com></a> Cc: Koenig, Christian <a class="moz-txt-link-rfc2396E" href="mailto:Christian.Koenig@amd.com"><Christian.Koenig@amd.com></a>; Liu, Leo <a class="moz-txt-link-rfc2396E" href="mailto:Leo.Liu@amd.com"><Leo.Liu@amd.com></a>; Jiang, Sonny <a class="moz-txt-link-rfc2396E" href="mailto:Sonny.Jiang@amd.com"><Sonny.Jiang@amd.com></a>; Dong, Ruijing <a class="moz-txt-link-rfc2396E" href="mailto:Ruijing.Dong@amd.com"><Ruijing.Dong@amd.com></a> Subject: [PATCH v1 1/8] drm/amdgpu: read back register after written The addition of register read-back in VCN v1.0 is intended to prevent potential race conditions. Signed-off-by: David (Ming Qiang) Wu <a class="moz-txt-link-rfc2396E" href="mailto:David.Wu3@amd.com"><David.Wu3@amd.com></a> --- drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c index 21b57c29bf7d..f56b623713c9 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c @@ -1009,6 +1009,11 @@ static int vcn_v1_0_start_spg_mode(struct amdgpu_vcn_inst *vinst) jpeg_v1_0_start(adev, 0); + /* Keeping one read-back to ensure all register writes are done, otherwise + * it may introduce race conditions + */ + RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR); + return 0; } @@ -1154,6 +1159,11 @@ static int vcn_v1_0_start_dpg_mode(struct amdgpu_vcn_inst *vinst) jpeg_v1_0_start(adev, 1); + /* Keeping one read-back to ensure all register writes are done, otherwise + * it may introduce race conditions + */ + RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR); + return 0; } -- 2.49.0 </pre> </blockquote> </body> </html>