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[AMD Official Use Only - AMD Internal Distribution Only]<br>
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This ignore these patches.</div>
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The series were sent prematurely.</div>
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<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> IVAN.LIPSKI@amd.com <IVAN.LIPSKI@amd.com><br>
<b>Sent:</b> Monday, July 7, 2025 3:41 PM<br>
<b>To:</b> amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org><br>
<b>Cc:</b> Wentland, Harry <Harry.Wentland@amd.com>; Li, Sun peng (Leo) <Sunpeng.Li@amd.com>; Pillai, Aurabindo <Aurabindo.Pillai@amd.com>; Li, Roman <Roman.Li@amd.com>; Lin, Wayne <Wayne.Lin@amd.com>; Chung, ChiaHsuan (Tom) <ChiaHsuan.Chung@amd.com>; Zuo,
Jerry <Jerry.Zuo@amd.com>; Wheeler, Daniel <Daniel.Wheeler@amd.com>; Wu, Ray <Ray.Wu@amd.com>; Hung, Alex <Alex.Hung@amd.com>; LIPSKI, IVAN <IVAN.LIPSKI@amd.com><br>
<b>Subject:</b> [PATCH 00/17] DC Patches July 7, 2025</font>
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<div class="PlainText">From: Ivan Lipski <ivan.lipski@amd.com><br>
<br>
start from:<br>
261fdc003175671fbda47d94d2244ba8c22934f5<br>
Workaround for stuck I2C arbitrage<br>
<br>
Stopped at:<br>
a69637b2e3b0ee50bd1bd10552115bbe1dfe2793<br>
Revert "Add DPP & HUBP reset if power gate enabled on DCN314"<br>
<br>
Please, pay extra attention to the following patches:<br>
<br>
1) drm/amd/display: MPC basic allocation logic and TMZ<br>
Changed the commit message.<br>
<br>
2) IP_CHECK_BODY drm/amd/display: refactor DSC cap calculations<br>
This commit message was pointed out with IP_CHECK_BODY; however,<br>
everything looks fine to me. Please take extra attention to this<br>
patch.<br>
<br>
3) drm/amd/display: Notify display idle on D3<br>
The patch seems to be more related to DCN42.<br>
<br>
4) drm/amd/display: Adding missing driver code for IPSv2.0<br>
The patch seems to be more related to DCN42.<br>
<br>
5) drm/amd/display: Notify DMUB on HW Release<br>
The patch seems to be more related to DCN42.<br>
<br>
6) drm/amd/display: Added static pg implementations for future use<br>
Changed the commit message.<br>
The patch seems to be more related to DCN42.<br>
<br>
7) drm/amd/display: Free memory allocation<br>
Was initially SOB'd by Jenkins Infra account (sw.jenkins),<br>
changed it to Clayton King<br>
<br>
8) IP_CHECK_BODY drm/amd/display: initial support for SmartMux<br>
Manually added 4 files:<br>
- dcn30m_clk_mgr.c<br>
- dcn30m_clk_mgr.h<br>
- dcn30m_clk_mgr_smu_msg.c<br>
- dcn30m_clk_mgr_smu_msg.h<br>
This commit message was pointed out with IP_CHECK_BODY; however,<br>
everything looks fine to me. Please take extra attention to this<br>
patch.<br>
<br>
<br>
Extra Note:<br>
1) IP_CHECK_BODY drm/amd/display: unit test framework with xmake.<br>
Dropped this patch.<br>
<br>
2) PROMOTION_SUBMODULE_PREFIX-dc/sspl-END- IP_CHECK_MSG<br>
Dropped this patch.<br>
<br>
<br>
<br>
Aurabindo Pillai (1):<br>
IP_CHECK_BODY drm/amd/display: initial support for SmartMux<br>
<br>
Charlene Liu (1):<br>
drm/amd/display: limit clear_update_flags to dcn32 and above<br>
<br>
Dillon Varone (1):<br>
IP_CHECK_BODY drm/amd/display: refactor DSC cap calculations<br>
<br>
Duncan Ma (2):<br>
drm/amd/display: Notify display idle on D3<br>
drm/amd/display: Notify DMUB on HW Release<br>
<br>
Fudongwang (1):<br>
drm/amd/display: Monitor patch to ignore EDID audio SAB check<br>
<br>
Ilya Bakoulin (1):<br>
drm/amd/display: Add definitions to support DID Type5 descriptors<br>
<br>
Ivan Lipski (1):<br>
drm/amd/display: Revert "Add DPP & HUBP reset if power gate enabled on<br>
DCN314"<br>
<br>
Jenkins, Sw (1):<br>
drm/amd/display: Free memory allocation<br>
<br>
Karthi Kandasamy (1):<br>
drm/amd/display: prepare for new platform<br>
<br>
Leo Chen (3):<br>
drm/amd/display: Adding missing driver code for IPSv2.0<br>
drm/amd/display: Added static pg implementations for future use<br>
drm/amd/display: New Behavior for debug option disable_ips_in_vpb<br>
<br>
Michael Strauss (1):<br>
drm/amd/display: Fix FIXED_VS retimer clock gen source override<br>
<br>
Ovidiu Bunea (2):<br>
drm/amd/display: Add support for Panel Replay on DP1 eDP<br>
(panel_inst=1)<br>
drm/amd/display: Add HPO encoder support to Replay<br>
<br>
Yihan Zhu (1):<br>
drm/amd/display: MPC basic allocation logic and TMZ<br>
<br>
.../gpu/drm/amd/display/dc/clk_mgr/Makefile | 2 +-<br>
.../gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c | 2 +-<br>
.../drm/amd/display/dc/clk_mgr/dcn30/dalsmc.h | 3 +-<br>
.../display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c | 4 +-<br>
.../display/dc/clk_mgr/dcn30/dcn30m_clk_mgr.c | 36 ++++<br>
.../display/dc/clk_mgr/dcn30/dcn30m_clk_mgr.h | 31 +++<br>
.../dc/clk_mgr/dcn30/dcn30m_clk_mgr_smu_msg.c | 118 +++++++++++<br>
.../dc/clk_mgr/dcn30/dcn30m_clk_mgr_smu_msg.h | 34 ++++<br>
.../dc/clk_mgr/dcn401/dcn401_clk_mgr.c | 33 ++-<br>
.../dc/clk_mgr/dcn401/dcn401_clk_mgr.h | 2 +<br>
drivers/gpu/drm/amd/display/dc/core/dc.c | 16 +-<br>
.../drm/amd/display/dc/core/dc_hw_sequencer.c | 26 +++<br>
.../gpu/drm/amd/display/dc/core/dc_resource.c | 4 +-<br>
.../gpu/drm/amd/display/dc/core/dc_state.c | 2 +<br>
.../gpu/drm/amd/display/dc/core/dc_stream.c | 67 ++++++<br>
drivers/gpu/drm/amd/display/dc/dc.h | 23 +++<br>
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 75 +++++--<br>
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h | 6 +<br>
drivers/gpu/drm/amd/display/dc/dc_stream.h | 11 +<br>
drivers/gpu/drm/amd/display/dc/dc_types.h | 3 +<br>
.../gpu/drm/amd/display/dc/dce/dmub_replay.c | 43 +++-<br>
.../gpu/drm/amd/display/dc/dce/dmub_replay.h | 2 +-<br>
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 192 +++++++++++++++---<br>
.../amd/display/dc/dsc/dcn401/dcn401_dsc.c | 24 +--<br>
.../amd/display/dc/dsc/dcn401/dcn401_dsc.h | 1 -<br>
drivers/gpu/drm/amd/display/dc/dsc/dsc.h | 1 +<br>
.../amd/display/dc/hubp/dcn401/dcn401_hubp.c | 4 +-<br>
.../amd/display/dc/hubp/dcn401/dcn401_hubp.h | 2 +-<br>
.../amd/display/dc/hwss/dce110/dce110_hwseq.c | 24 +++<br>
.../amd/display/dc/hwss/dcn10/dcn10_hwseq.c | 2 +-<br>
.../amd/display/dc/hwss/dcn31/dcn31_hwseq.c | 13 ++<br>
.../amd/display/dc/hwss/dcn314/dcn314_hwseq.c | 37 +---<br>
.../amd/display/dc/hwss/dcn314/dcn314_hwseq.h | 2 -<br>
.../amd/display/dc/hwss/dcn314/dcn314_init.c | 2 +-<br>
.../amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 14 +-<br>
.../amd/display/dc/hwss/dcn401/dcn401_hwseq.h | 1 +<br>
.../drm/amd/display/dc/hwss/hw_sequencer.h | 3 +<br>
.../gpu/drm/amd/display/dc/inc/core_types.h | 3 +<br>
.../gpu/drm/amd/display/dc/inc/hw/clk_mgr.h | 14 ++<br>
drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h | 2 +-<br>
.../gpu/drm/amd/display/dc/inc/hw/pg_cntl.h | 2 +<br>
.../link_hwss_hpo_fixed_vs_pe_retimer_dp.c | 2 +-<br>
.../gpu/drm/amd/display/dc/link/link_dpms.c | 19 +-<br>
.../drm/amd/display/dc/link/link_factory.c | 8 +-<br>
.../dc/link/protocols/link_dp_capability.c | 19 ++<br>
.../link/protocols/link_edp_panel_control.c | 19 +-<br>
.../link/protocols/link_edp_panel_control.h | 1 +<br>
.../dc/resource/dcn20/dcn20_resource.c | 2 +<br>
.../dc/resource/dcn201/dcn201_resource.c | 2 +<br>
.../dc/resource/dcn21/dcn21_resource.c | 2 +<br>
.../dc/resource/dcn30/dcn30_resource.c | 2 +<br>
.../dc/resource/dcn301/dcn301_resource.c | 2 +<br>
.../dc/resource/dcn302/dcn302_resource.c | 2 +<br>
.../dc/resource/dcn303/dcn303_resource.c | 2 +<br>
.../dc/resource/dcn31/dcn31_resource.c | 2 +<br>
.../dc/resource/dcn314/dcn314_resource.c | 2 +<br>
.../dc/resource/dcn315/dcn315_resource.c | 2 +<br>
.../dc/resource/dcn316/dcn316_resource.c | 2 +<br>
.../dc/resource/dcn32/dcn32_resource.c | 2 +<br>
.../dc/resource/dcn321/dcn321_resource.c | 2 +<br>
.../dc/resource/dcn35/dcn35_resource.c | 2 +<br>
.../dc/resource/dcn351/dcn351_resource.c | 2 +<br>
.../dc/resource/dcn36/dcn36_resource.c | 2 +<br>
.../dc/resource/dcn401/dcn401_resource.c | 2 +<br>
.../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 36 +++-<br>
.../amd/display/modules/power/power_helpers.h | 2 +<br>
66 files changed, 902 insertions(+), 124 deletions(-)<br>
create mode 100644 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30m_clk_mgr.c<br>
create mode 100644 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30m_clk_mgr.h<br>
create mode 100644 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30m_clk_mgr_smu_msg.c<br>
create mode 100644 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30m_clk_mgr_smu_msg.h<br>
<br>
-- <br>
2.43.0<br>
<br>
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