[Beignet] [PATCH V2 2/6] Build the constant base address propagation registers.

[Yang Rong]

Signed-off-by: Yang Rong <rong.r.yang at intel.com>
---
 backend/src/backend/context.cpp |   29 +++++++++++++++++++++++++++++
 backend/src/backend/context.hpp |    8 ++++++++
 2 files changed, 37 insertions(+)

diff --git a/backend/src/backend/context.cpp b/backend/src/backend/context.cpp
index c3ddb59..0a26b3d 100644
--- a/backend/src/backend/context.cpp
+++ b/backend/src/backend/context.cpp
@@ -295,6 +295,7 @@ namespace gbe
     this->buildJIPs();
     this->buildStack();
     this->handleSLM();
+    this->buildConstBufs();
     if (this->emitCode() == false) {
       GBE_DELETE(this->kernel);
       this->kernel = NULL;
@@ -548,6 +549,34 @@ namespace gbe
     kernel->useSLM = useSLM;
   }
 
+  void Context::buildConstBufs(void) {
+    uint32_t argNum = fn.argNum();
+    for (uint32_t argID = 0; argID < argNum; ++argID) {
+      const auto &arg = fn.getArg(argID);
+
+      if(arg.type != ir::FunctionArgument::CONSTANT_POINTER)
+        continue;
+
+      ir::Register srcReg = arg.reg;
+      constBaseProps.insert(std::make_pair(srcReg, srcReg));
+
+      //build the const Propagation registers
+      fn.foreachInstruction([this](const ir::Instruction &insn) {
+        using namespace ir;
+        if(insn.getOpcode() == OP_LOAD) return;
+        const uint32_t srcNum = insn.getSrcNum();
+        for (uint32_t srcID = 0; srcID < srcNum; ++srcID) {
+          const ir::Register reg = insn.getSrc(srcID);
+          if((constBaseProps.contains(reg) != false)) {
+            const ir::Register dstReg = insn.getDst();
+            constBaseProps.insert(std::make_pair(dstReg, constBaseProps.find(reg)->second));
+            break;
+          }
+        }
+      });
+    }
+  }
+
   bool Context::isScalarReg(const ir::Register &reg) const {
     GBE_ASSERT(fn.getProfile() == ir::Profile::PROFILE_OCL);
     if (fn.getArg(reg) != NULL) return true;
diff --git a/backend/src/backend/context.hpp b/backend/src/backend/context.hpp
index 55a63a7..3b6e635 100644
--- a/backend/src/backend/context.hpp
+++ b/backend/src/backend/context.hpp
@@ -82,6 +82,10 @@ namespace gbe
     INLINE bool hasJIP(const ir::Instruction *insn) const {
       return JIPs.find(insn) != JIPs.end();
     }
+    INLINE ir::Register getConstBaseReg(const ir::Register reg) const {
+      GBE_ASSERT(constBaseProps.find(reg) != constBaseProps.end());
+      return constBaseProps.find(reg)->second;
+    }
     /*! Allocate some memory in the register file */
     int16_t allocate(int16_t size, int16_t alignment);
     /*! Deallocate previously allocated memory */
@@ -105,12 +109,15 @@ namespace gbe
     void buildJIPs(void);
     /*! Configure SLM use if needed */
     void handleSLM(void);
+    /* Build constant buffer map */
+    void buildConstBufs(void);
     /*! Insert a new entry with the given size in the Curbe. Return the offset
      *  of the entry
      */
     void newCurbeEntry(gbe_curbe_type value, uint32_t subValue, uint32_t size, uint32_t alignment = 0);
     /*! Provide for each branch and label the label index target */
     typedef map<const ir::Instruction*, ir::LabelIndex> JIPMap;
+    typedef map<const ir::Register, ir::Register> ConstBasePropMap;
     const ir::Unit &unit;                 //!< Unit that contains the kernel
     const ir::Function &fn;               //!< Function to compile
     std::string name;                     //!< Name of the kernel to compile
@@ -120,6 +127,7 @@ namespace gbe
     RegisterFilePartitioner *partitioner; //!< Handle register file partionning
     set<ir::LabelIndex> usedLabels;       //!< Set of all used labels
     JIPMap JIPs;                          //!< Where to jump all labels/branches
+    ConstBasePropMap constBaseProps;      //!< const buffer reg propagation regs
     uint32_t simdWidth;                   //!< Number of lanes per HW threads
     GBE_CLASS(Context);                   //!< Use custom allocators
   };
-- 
1.7.9.5