[Beignet] [PATCH 1/9] support 64bit-integer reading(writing)
Homer Hsing
homer.xing at intel.com
Sun Aug 4 22:06:35 PDT 2013
Signed-off-by: Homer Hsing <homer.xing at intel.com>
---
backend/src/backend/gen_context.cpp | 8 +++---
backend/src/backend/gen_context.hpp | 4 +--
backend/src/backend/gen_encoder.cpp | 4 +--
backend/src/backend/gen_encoder.hpp | 8 +++---
.../src/backend/gen_insn_gen7_schedule_info.hxx | 4 +--
backend/src/backend/gen_insn_selection.cpp | 30 ++++++++++++----------
backend/src/backend/gen_insn_selection.hxx | 4 +--
backend/src/ir/instruction.cpp | 1 +
backend/src/llvm/llvm_gen_backend.cpp | 2 +-
9 files changed, 34 insertions(+), 31 deletions(-)
diff --git a/backend/src/backend/gen_context.cpp b/backend/src/backend/gen_context.cpp
index 56f6b2b..83011cb 100644
--- a/backend/src/backend/gen_context.cpp
+++ b/backend/src/backend/gen_context.cpp
@@ -354,12 +354,12 @@ namespace gbe
p->pop();
}
- void GenContext::emitReadFloat64Instruction(const SelectionInstruction &insn) {
+ void GenContext::emitRead64Instruction(const SelectionInstruction &insn) {
const GenRegister dst = ra->genReg(insn.dst(0));
const GenRegister src = ra->genReg(insn.src(0));
const uint32_t bti = insn.extra.function;
const uint32_t elemNum = insn.extra.elem;
- p->READ_FLOAT64(dst, src, bti, elemNum);
+ p->READ64(dst, src, bti, elemNum);
}
void GenContext::emitUntypedReadInstruction(const SelectionInstruction &insn) {
@@ -370,11 +370,11 @@ namespace gbe
p->UNTYPED_READ(dst, src, bti, elemNum);
}
- void GenContext::emitWriteFloat64Instruction(const SelectionInstruction &insn) {
+ void GenContext::emitWrite64Instruction(const SelectionInstruction &insn) {
const GenRegister src = ra->genReg(insn.src(0));
const uint32_t bti = insn.extra.function;
const uint32_t elemNum = insn.extra.elem;
- p->WRITE_FLOAT64(src, bti, elemNum);
+ p->WRITE64(src, bti, elemNum);
}
void GenContext::emitUntypedWriteInstruction(const SelectionInstruction &insn) {
diff --git a/backend/src/backend/gen_context.hpp b/backend/src/backend/gen_context.hpp
index 5dfaef9..82d41b6 100644
--- a/backend/src/backend/gen_context.hpp
+++ b/backend/src/backend/gen_context.hpp
@@ -87,8 +87,8 @@ namespace gbe
void emitBarrierInstruction(const SelectionInstruction &insn);
void emitFenceInstruction(const SelectionInstruction &insn);
void emitMathInstruction(const SelectionInstruction &insn);
- void emitReadFloat64Instruction(const SelectionInstruction &insn);
- void emitWriteFloat64Instruction(const SelectionInstruction &insn);
+ void emitRead64Instruction(const SelectionInstruction &insn);
+ void emitWrite64Instruction(const SelectionInstruction &insn);
void emitUntypedReadInstruction(const SelectionInstruction &insn);
void emitUntypedWriteInstruction(const SelectionInstruction &insn);
void emitAtomicInstruction(const SelectionInstruction &insn);
diff --git a/backend/src/backend/gen_encoder.cpp b/backend/src/backend/gen_encoder.cpp
index 0a2b673..33f5950 100644
--- a/backend/src/backend/gen_encoder.cpp
+++ b/backend/src/backend/gen_encoder.cpp
@@ -365,7 +365,7 @@ namespace gbe
return 0;
}
- void GenEncoder::READ_FLOAT64(GenRegister dst, GenRegister src, uint32_t bti, uint32_t elemNum) {
+ void GenEncoder::READ64(GenRegister dst, GenRegister src, uint32_t bti, uint32_t elemNum) {
int w = curr.execWidth;
dst.type = GEN_TYPE_UD;
src.type = GEN_TYPE_UD;
@@ -408,7 +408,7 @@ namespace gbe
pop();
}
- void GenEncoder::WRITE_FLOAT64(GenRegister msg, uint32_t bti, uint32_t elemNum) {
+ void GenEncoder::WRITE64(GenRegister msg, uint32_t bti, uint32_t elemNum) {
int w = curr.execWidth;
GenRegister r = GenRegister::retype(GenRegister::suboffset(msg, w*3), GEN_TYPE_UD);
r.type = GEN_TYPE_UD;
diff --git a/backend/src/backend/gen_encoder.hpp b/backend/src/backend/gen_encoder.hpp
index d3a7165..cd8990e 100644
--- a/backend/src/backend/gen_encoder.hpp
+++ b/backend/src/backend/gen_encoder.hpp
@@ -141,10 +141,10 @@ namespace gbe
void WAIT(void);
/*! Atomic instructions */
void ATOMIC(GenRegister dst, uint32_t function, GenRegister src, uint32_t bti, uint32_t srcNum);
- /*! Read 64-bits float arrays */
- void READ_FLOAT64(GenRegister dst, GenRegister src, uint32_t bti, uint32_t elemNum);
- /*! Write 64-bits float arrays */
- void WRITE_FLOAT64(GenRegister src, uint32_t bti, uint32_t elemNum);
+ /*! Read 64-bits float/int arrays */
+ void READ64(GenRegister dst, GenRegister src, uint32_t bti, uint32_t elemNum);
+ /*! Write 64-bits float/int arrays */
+ void WRITE64(GenRegister src, uint32_t bti, uint32_t elemNum);
/*! Untyped read (upto 4 channels) */
void UNTYPED_READ(GenRegister dst, GenRegister src, uint32_t bti, uint32_t elemNum);
/*! Untyped write (upto 4 channels) */
diff --git a/backend/src/backend/gen_insn_gen7_schedule_info.hxx b/backend/src/backend/gen_insn_gen7_schedule_info.hxx
index f3f4a25..6f37c3d 100644
--- a/backend/src/backend/gen_insn_gen7_schedule_info.hxx
+++ b/backend/src/backend/gen_insn_gen7_schedule_info.hxx
@@ -12,8 +12,8 @@ DECL_GEN7_SCHEDULE(Wait, 20, 2, 2)
DECL_GEN7_SCHEDULE(Math, 20, 4, 2)
DECL_GEN7_SCHEDULE(Barrier, 80, 1, 1)
DECL_GEN7_SCHEDULE(Fence, 80, 1, 1)
-DECL_GEN7_SCHEDULE(ReadFloat64, 80, 1, 1)
-DECL_GEN7_SCHEDULE(WriteFloat64, 80, 1, 1)
+DECL_GEN7_SCHEDULE(Read64, 80, 1, 1)
+DECL_GEN7_SCHEDULE(Write64, 80, 1, 1)
DECL_GEN7_SCHEDULE(UntypedRead, 80, 1, 1)
DECL_GEN7_SCHEDULE(UntypedWrite, 80, 1, 1)
DECL_GEN7_SCHEDULE(ByteGather, 80, 1, 1)
diff --git a/backend/src/backend/gen_insn_selection.cpp b/backend/src/backend/gen_insn_selection.cpp
index d4be8bf..b1c9cfb 100644
--- a/backend/src/backend/gen_insn_selection.cpp
+++ b/backend/src/backend/gen_insn_selection.cpp
@@ -167,14 +167,14 @@ namespace gbe
bool SelectionInstruction::isRead(void) const {
return this->opcode == SEL_OP_UNTYPED_READ ||
- this->opcode == SEL_OP_READ_FLOAT64 ||
+ this->opcode == SEL_OP_READ64 ||
this->opcode == SEL_OP_ATOMIC ||
this->opcode == SEL_OP_BYTE_GATHER;
}
bool SelectionInstruction::isWrite(void) const {
return this->opcode == SEL_OP_UNTYPED_WRITE ||
- this->opcode == SEL_OP_WRITE_FLOAT64 ||
+ this->opcode == SEL_OP_WRITE64 ||
this->opcode == SEL_OP_ATOMIC ||
this->opcode == SEL_OP_BYTE_SCATTER;
}
@@ -466,9 +466,9 @@ namespace gbe
/*! Atomic instruction */
void ATOMIC(Reg dst, uint32_t function, uint32_t srcNum, Reg src0, Reg src1, Reg src2, uint32_t bti);
/*! Read 64 bits float array */
- void READ_FLOAT64(Reg addr, const GenRegister *dst, uint32_t elemNum, uint32_t bti);
+ void READ64(Reg addr, const GenRegister *dst, uint32_t elemNum, uint32_t bti);
/*! Write 64 bits float array */
- void WRITE_FLOAT64(Reg addr, const GenRegister *src, uint32_t elemNum, uint32_t bti);
+ void WRITE64(Reg addr, const GenRegister *src, uint32_t elemNum, uint32_t bti);
/*! Untyped read (up to 4 elements) */
void UNTYPED_READ(Reg addr, const GenRegister *dst, uint32_t elemNum, uint32_t bti);
/*! Untyped write (up to 4 elements) */
@@ -760,12 +760,12 @@ namespace gbe
void Selection::Opaque::NOP(void) { this->appendInsn(SEL_OP_NOP, 0, 0); }
void Selection::Opaque::WAIT(void) { this->appendInsn(SEL_OP_WAIT, 0, 0); }
- void Selection::Opaque::READ_FLOAT64(Reg addr,
+ void Selection::Opaque::READ64(Reg addr,
const GenRegister *dst,
uint32_t elemNum,
uint32_t bti)
{
- SelectionInstruction *insn = this->appendInsn(SEL_OP_READ_FLOAT64, elemNum, 1);
+ SelectionInstruction *insn = this->appendInsn(SEL_OP_READ64, elemNum, 1);
SelectionVector *srcVector = this->appendVector();
SelectionVector *dstVector = this->appendVector();
@@ -814,12 +814,12 @@ namespace gbe
srcVector->reg = &insn->src(0);
}
- void Selection::Opaque::WRITE_FLOAT64(Reg addr,
+ void Selection::Opaque::WRITE64(Reg addr,
const GenRegister *src,
uint32_t elemNum,
uint32_t bti)
{
- SelectionInstruction *insn = this->appendInsn(SEL_OP_WRITE_FLOAT64, 0, elemNum+1);
+ SelectionInstruction *insn = this->appendInsn(SEL_OP_WRITE64, 0, elemNum+1);
SelectionVector *vector = this->appendVector();
// Regular instruction to encode
@@ -1832,6 +1832,8 @@ namespace gbe
using namespace ir;
switch (type) {
case TYPE_DOUBLE:
+ case TYPE_S64:
+ case TYPE_U64:
return GEN_BYTE_SCATTER_QWORD;
case TYPE_FLOAT:
case TYPE_U32:
@@ -1864,7 +1866,7 @@ namespace gbe
sel.UNTYPED_READ(addr, dst.data(), valueNum, bti);
}
- void emitReadFloat64(Selection::Opaque &sel,
+ void emitRead64(Selection::Opaque &sel,
const ir::LoadInstruction &insn,
GenRegister addr,
uint32_t bti) const
@@ -1877,7 +1879,7 @@ namespace gbe
dst.push_back(sel.selReg(sel.reg(FAMILY_QWORD)));
if (sel.ctx.getSimdWidth() == 16)
dst.push_back(sel.selReg(sel.reg(FAMILY_QWORD)));
- sel.READ_FLOAT64(addr, dst.data(), dst.size(), bti);
+ sel.READ64(addr, dst.data(), dst.size(), bti);
}
void emitByteGather(Selection::Opaque &sel,
@@ -1932,7 +1934,7 @@ namespace gbe
if (insn.getAddressSpace() == MEM_CONSTANT)
this->emitIndirectMove(sel, insn, address);
else if (insn.isAligned() == true && elemSize == GEN_BYTE_SCATTER_QWORD)
- this->emitReadFloat64(sel, insn, address, space == MEM_LOCAL ? 0xfe : 0x00);
+ this->emitRead64(sel, insn, address, space == MEM_LOCAL ? 0xfe : 0x00);
else if (insn.isAligned() == true && elemSize == GEN_BYTE_SCATTER_DWORD)
this->emitUntypedRead(sel, insn, address, space == MEM_LOCAL ? 0xfe : 0x00);
else {
@@ -1963,7 +1965,7 @@ namespace gbe
sel.UNTYPED_WRITE(addr, value.data(), valueNum, bti);
}
- void emitWriteFloat64(Selection::Opaque &sel,
+ void emitWrite64(Selection::Opaque &sel,
const ir::StoreInstruction &insn,
uint32_t bti) const
{
@@ -1979,7 +1981,7 @@ namespace gbe
value.push_back(sel.selReg(sel.reg(FAMILY_QWORD)));
if (sel.ctx.getSimdWidth() == 16)
value.push_back(sel.selReg(sel.reg(FAMILY_QWORD)));
- sel.WRITE_FLOAT64(addr, value.data(), value.size(), bti);
+ sel.WRITE64(addr, value.data(), value.size(), bti);
}
void emitByteScatter(Selection::Opaque &sel,
@@ -2012,7 +2014,7 @@ namespace gbe
const Type type = insn.getValueType();
const uint32_t elemSize = getByteScatterGatherSize(type);
if (insn.isAligned() == true && elemSize == GEN_BYTE_SCATTER_QWORD)
- this->emitWriteFloat64(sel, insn, bti);
+ this->emitWrite64(sel, insn, bti);
else if (insn.isAligned() == true && elemSize == GEN_BYTE_SCATTER_DWORD)
this->emitUntypedWrite(sel, insn, bti);
else {
diff --git a/backend/src/backend/gen_insn_selection.hxx b/backend/src/backend/gen_insn_selection.hxx
index 33c3937..c6aede5 100644
--- a/backend/src/backend/gen_insn_selection.hxx
+++ b/backend/src/backend/gen_insn_selection.hxx
@@ -35,8 +35,8 @@ DECL_SELECTION_IR(BARRIER, BarrierInstruction)
DECL_SELECTION_IR(FENCE, FenceInstruction)
DECL_SELECTION_IR(UNTYPED_READ, UntypedReadInstruction)
DECL_SELECTION_IR(UNTYPED_WRITE, UntypedWriteInstruction)
-DECL_SELECTION_IR(READ_FLOAT64, ReadFloat64Instruction)
-DECL_SELECTION_IR(WRITE_FLOAT64, WriteFloat64Instruction)
+DECL_SELECTION_IR(READ64, Read64Instruction)
+DECL_SELECTION_IR(WRITE64, Write64Instruction)
DECL_SELECTION_IR(BYTE_GATHER, ByteGatherInstruction)
DECL_SELECTION_IR(BYTE_SCATTER, ByteScatterInstruction)
DECL_SELECTION_IR(SAMPLE, SampleInstruction)
diff --git a/backend/src/ir/instruction.cpp b/backend/src/ir/instruction.cpp
index 34df8d7..2589848 100644
--- a/backend/src/ir/instruction.cpp
+++ b/backend/src/ir/instruction.cpp
@@ -664,6 +664,7 @@ namespace ir {
static const Type allButBool[] = {TYPE_S8, TYPE_U8,
TYPE_S16, TYPE_U16,
TYPE_S32, TYPE_U32,
+ TYPE_S64, TYPE_U64,
TYPE_FLOAT, TYPE_DOUBLE};
static const uint32_t allButBoolNum = ARRAY_ELEM_NUM(allButBool);
diff --git a/backend/src/llvm/llvm_gen_backend.cpp b/backend/src/llvm/llvm_gen_backend.cpp
index c8c5484..47d59c5 100644
--- a/backend/src/llvm/llvm_gen_backend.cpp
+++ b/backend/src/llvm/llvm_gen_backend.cpp
@@ -2371,7 +2371,7 @@ namespace gbe
// Scalar is easy. We neednot build register tuples
if (isScalarType(llvmType) == true) {
const ir::Type type = getType(ctx, llvmType);
- if(type == ir::TYPE_DOUBLE) // 64bit-float load(store) don't support SIMD16
+ if(type == ir::TYPE_DOUBLE || type == ir::TYPE_S64 || type == ir::TYPE_U64) // 64bit load(store) doesn't support SIMD16
OCL_SIMD_WIDTH = 8;
const ir::Register values = this->getRegister(llvmValues);
if (isLoad)
--
1.8.1.2
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