[Beignet] [PATCH 1/3] support 64bit-integer immediate value

[Homer Hsing]

Signed-off-by: Homer Hsing <homer.xing at intel.com>
---
 backend/src/backend/gen_context.cpp        |  1 +
 backend/src/backend/gen_encoder.cpp        | 22 ++++++++++++++++++++++
 backend/src/backend/gen_encoder.hpp        |  1 +
 backend/src/backend/gen_insn_selection.cpp |  3 +++
 backend/src/backend/gen_insn_selection.hxx |  1 +
 backend/src/backend/gen_register.hpp       |  7 +++++++
 6 files changed, 35 insertions(+)

diff --git a/backend/src/backend/gen_context.cpp b/backend/src/backend/gen_context.cpp
index ef30eee..69dab85 100644
--- a/backend/src/backend/gen_context.cpp
+++ b/backend/src/backend/gen_context.cpp
@@ -146,6 +146,7 @@ namespace gbe
       case SEL_OP_RNDU: p->RNDU(dst, src); break;
       case SEL_OP_RNDE: p->RNDE(dst, src); break;
       case SEL_OP_RNDZ: p->RNDZ(dst, src); break;
+      case SEL_OP_LOAD_INT64_IMM: p->LOAD_INT64_IMM(dst, src.value.i64); break;
       default: NOT_IMPLEMENTED;
     }
   }
diff --git a/backend/src/backend/gen_encoder.cpp b/backend/src/backend/gen_encoder.cpp
index 64b5bd1..2545fb7 100644
--- a/backend/src/backend/gen_encoder.cpp
+++ b/backend/src/backend/gen_encoder.cpp
@@ -821,6 +821,28 @@ namespace gbe
     MOV(dest, src0);
   }
 
+  void GenEncoder::LOAD_INT64_IMM(GenRegister dest, int64_t value) {
+    GenRegister u0 = GenRegister::immd((int)value), u1 = GenRegister::immd(value >> 32);
+    int execWidth = curr.execWidth;
+    push();
+    curr.execWidth = 8;
+    MOV(dest.top_half(), u1);
+    MOV(dest.bottom_half(), u0);
+    curr.nibControl = 1;
+    MOV(GenRegister::suboffset(dest, 4).top_half(), u1);
+    MOV(GenRegister::suboffset(dest, 4).bottom_half(), u0);
+    if (execWidth == 16) {
+      curr.quarterControl = 1;
+      curr.nibControl = 0;
+      MOV(GenRegister::suboffset(dest, 8).top_half(), u1);
+      MOV(GenRegister::suboffset(dest, 8).bottom_half(), u0);
+      curr.nibControl = 1;
+      MOV(GenRegister::suboffset(dest, 12).top_half(), u1);
+      MOV(GenRegister::suboffset(dest, 12).bottom_half(), u0);
+    }
+    pop();
+  }
+
   void GenEncoder::MOV_DF(GenRegister dest, GenRegister src0, GenRegister r) {
     int w = curr.execWidth;
     if (src0.isdf()) {
diff --git a/backend/src/backend/gen_encoder.hpp b/backend/src/backend/gen_encoder.hpp
index 083bd8c..54674d3 100644
--- a/backend/src/backend/gen_encoder.hpp
+++ b/backend/src/backend/gen_encoder.hpp
@@ -125,6 +125,7 @@ namespace gbe
 #undef ALU3
     void MOV_DF(GenRegister dest, GenRegister src0, GenRegister tmp = GenRegister::null());
     void LOAD_DF_IMM(GenRegister dest, GenRegister tmp, double value);
+    void LOAD_INT64_IMM(GenRegister dest, int64_t value);
     /*! Barrier message (to synchronize threads of a workgroup) */
     void BARRIER(GenRegister src);
     /*! Memory fence message (to order loads and stores between threads) */
diff --git a/backend/src/backend/gen_insn_selection.cpp b/backend/src/backend/gen_insn_selection.cpp
index eca62b4..66cfa31 100644
--- a/backend/src/backend/gen_insn_selection.cpp
+++ b/backend/src/backend/gen_insn_selection.cpp
@@ -415,6 +415,7 @@ namespace gbe
     ALU1(MOV)
     ALU2(MOV_DF)
     ALU2(LOAD_DF_IMM)
+    ALU1(LOAD_INT64_IMM)
     ALU1(RNDZ)
     ALU1(RNDE)
     ALU2(SEL)
@@ -1806,6 +1807,8 @@ namespace gbe
         case TYPE_U8:  sel.MOV(dst, GenRegister::immuw(imm.data.u8)); break;
         case TYPE_S8:  sel.MOV(dst, GenRegister::immw(imm.data.s8)); break;
         case TYPE_DOUBLE: sel.LOAD_DF_IMM(dst, GenRegister::immdf(imm.data.f64), sel.selReg(sel.reg(FAMILY_QWORD))); break;
+        case TYPE_S64: sel.LOAD_INT64_IMM(dst, GenRegister::immint64(imm.data.s64)); break;
+        case TYPE_U64: sel.LOAD_INT64_IMM(dst, GenRegister::immint64(imm.data.u64)); break;
         default: NOT_SUPPORTED;
       }
       sel.pop();
diff --git a/backend/src/backend/gen_insn_selection.hxx b/backend/src/backend/gen_insn_selection.hxx
index f2b86c4..8eeb19f 100644
--- a/backend/src/backend/gen_insn_selection.hxx
+++ b/backend/src/backend/gen_insn_selection.hxx
@@ -2,6 +2,7 @@ DECL_SELECTION_IR(LABEL, LabelInstruction)
 DECL_SELECTION_IR(MOV, UnaryInstruction)
 DECL_SELECTION_IR(MOV_DF, BinaryInstruction)
 DECL_SELECTION_IR(LOAD_DF_IMM, BinaryInstruction)
+DECL_SELECTION_IR(LOAD_INT64_IMM, UnaryInstruction)
 DECL_SELECTION_IR(NOT, UnaryInstruction)
 DECL_SELECTION_IR(LZD, UnaryInstruction)
 DECL_SELECTION_IR(RNDZ, UnaryInstruction)
diff --git a/backend/src/backend/gen_register.hpp b/backend/src/backend/gen_register.hpp
index fda2e6c..10c8a48 100644
--- a/backend/src/backend/gen_register.hpp
+++ b/backend/src/backend/gen_register.hpp
@@ -202,6 +202,7 @@ namespace gbe
       int32_t d;
       uint32_t ud;
       uint16_t reg;
+      int64_t i64;
     } value;
 
     uint32_t nr:8;         //!< Just for some physical registers (acc, null)
@@ -434,6 +435,12 @@ namespace gbe
                          GEN_HORIZONTAL_STRIDE_0);
     }
 
+    static INLINE GenRegister immint64(int64_t i) {
+      GenRegister immediate = imm(GEN_TYPE_L);
+      immediate.value.i64 = i;
+      return immediate;
+    }
+
     static INLINE GenRegister immdf(double df) {
       GenRegister immediate = imm(GEN_TYPE_DF);
       immediate.value.df = df;
-- 
1.8.1.2