[Beignet] [PATCH v3 1/3] support 64bit-integer immediate value
Zhigang Gong
zhigang.gong at gmail.com
Wed Aug 7 00:00:00 PDT 2013
LGTM, pushed all the three patches. Thanks.
On Wed, Aug 07, 2013 at 12:19:52PM +0800, Homer Hsing wrote:
> v3: folded similar code into a "for-loop"
>
> Signed-off-by: Homer Hsing <homer.xing at intel.com>
> ---
> backend/src/backend/gen_context.cpp | 1 +
> backend/src/backend/gen_encoder.cpp | 14 ++++++++++++++
> backend/src/backend/gen_encoder.hpp | 1 +
> backend/src/backend/gen_insn_selection.cpp | 3 +++
> backend/src/backend/gen_insn_selection.hxx | 1 +
> backend/src/backend/gen_register.hpp | 29 +++++++++++++++++++++++++++++
> 6 files changed, 49 insertions(+)
>
> diff --git a/backend/src/backend/gen_context.cpp b/backend/src/backend/gen_context.cpp
> index ef30eee..69dab85 100644
> --- a/backend/src/backend/gen_context.cpp
> +++ b/backend/src/backend/gen_context.cpp
> @@ -146,6 +146,7 @@ namespace gbe
> case SEL_OP_RNDU: p->RNDU(dst, src); break;
> case SEL_OP_RNDE: p->RNDE(dst, src); break;
> case SEL_OP_RNDZ: p->RNDZ(dst, src); break;
> + case SEL_OP_LOAD_INT64_IMM: p->LOAD_INT64_IMM(dst, src.value.i64); break;
> default: NOT_IMPLEMENTED;
> }
> }
> diff --git a/backend/src/backend/gen_encoder.cpp b/backend/src/backend/gen_encoder.cpp
> index 64b5bd1..3793d8b 100644
> --- a/backend/src/backend/gen_encoder.cpp
> +++ b/backend/src/backend/gen_encoder.cpp
> @@ -821,6 +821,20 @@ namespace gbe
> MOV(dest, src0);
> }
>
> + void GenEncoder::LOAD_INT64_IMM(GenRegister dest, int64_t value) {
> + GenRegister u0 = GenRegister::immd((int)value), u1 = GenRegister::immd(value >> 32);
> + int execWidth = curr.execWidth;
> + push();
> + curr.execWidth = 8;
> + for(int nib = 0; nib < execWidth/4; nib ++) {
> + curr.chooseNib(nib);
> + MOV(dest.top_half(), u1);
> + MOV(dest.bottom_half(), u0);
> + dest = GenRegister::suboffset(dest, 4);
> + }
> + pop();
> + }
> +
> void GenEncoder::MOV_DF(GenRegister dest, GenRegister src0, GenRegister r) {
> int w = curr.execWidth;
> if (src0.isdf()) {
> diff --git a/backend/src/backend/gen_encoder.hpp b/backend/src/backend/gen_encoder.hpp
> index 083bd8c..54674d3 100644
> --- a/backend/src/backend/gen_encoder.hpp
> +++ b/backend/src/backend/gen_encoder.hpp
> @@ -125,6 +125,7 @@ namespace gbe
> #undef ALU3
> void MOV_DF(GenRegister dest, GenRegister src0, GenRegister tmp = GenRegister::null());
> void LOAD_DF_IMM(GenRegister dest, GenRegister tmp, double value);
> + void LOAD_INT64_IMM(GenRegister dest, int64_t value);
> /*! Barrier message (to synchronize threads of a workgroup) */
> void BARRIER(GenRegister src);
> /*! Memory fence message (to order loads and stores between threads) */
> diff --git a/backend/src/backend/gen_insn_selection.cpp b/backend/src/backend/gen_insn_selection.cpp
> index eca62b4..66cfa31 100644
> --- a/backend/src/backend/gen_insn_selection.cpp
> +++ b/backend/src/backend/gen_insn_selection.cpp
> @@ -415,6 +415,7 @@ namespace gbe
> ALU1(MOV)
> ALU2(MOV_DF)
> ALU2(LOAD_DF_IMM)
> + ALU1(LOAD_INT64_IMM)
> ALU1(RNDZ)
> ALU1(RNDE)
> ALU2(SEL)
> @@ -1806,6 +1807,8 @@ namespace gbe
> case TYPE_U8: sel.MOV(dst, GenRegister::immuw(imm.data.u8)); break;
> case TYPE_S8: sel.MOV(dst, GenRegister::immw(imm.data.s8)); break;
> case TYPE_DOUBLE: sel.LOAD_DF_IMM(dst, GenRegister::immdf(imm.data.f64), sel.selReg(sel.reg(FAMILY_QWORD))); break;
> + case TYPE_S64: sel.LOAD_INT64_IMM(dst, GenRegister::immint64(imm.data.s64)); break;
> + case TYPE_U64: sel.LOAD_INT64_IMM(dst, GenRegister::immint64(imm.data.u64)); break;
> default: NOT_SUPPORTED;
> }
> sel.pop();
> diff --git a/backend/src/backend/gen_insn_selection.hxx b/backend/src/backend/gen_insn_selection.hxx
> index f2b86c4..8eeb19f 100644
> --- a/backend/src/backend/gen_insn_selection.hxx
> +++ b/backend/src/backend/gen_insn_selection.hxx
> @@ -2,6 +2,7 @@ DECL_SELECTION_IR(LABEL, LabelInstruction)
> DECL_SELECTION_IR(MOV, UnaryInstruction)
> DECL_SELECTION_IR(MOV_DF, BinaryInstruction)
> DECL_SELECTION_IR(LOAD_DF_IMM, BinaryInstruction)
> +DECL_SELECTION_IR(LOAD_INT64_IMM, UnaryInstruction)
> DECL_SELECTION_IR(NOT, UnaryInstruction)
> DECL_SELECTION_IR(LZD, UnaryInstruction)
> DECL_SELECTION_IR(RNDZ, UnaryInstruction)
> diff --git a/backend/src/backend/gen_register.hpp b/backend/src/backend/gen_register.hpp
> index fda2e6c..2cad4c0 100644
> --- a/backend/src/backend/gen_register.hpp
> +++ b/backend/src/backend/gen_register.hpp
> @@ -136,6 +136,28 @@ namespace gbe
> uint32_t predicate:4;
> uint32_t inversePredicate:1;
> uint32_t saturate:1;
> + void chooseNib(int nib) {
> + switch (nib) {
> + case 0:
> + quarterControl = 0;
> + nibControl = 0;
> + break;
> + case 1:
> + quarterControl = 0;
> + nibControl = 1;
> + break;
> + case 2:
> + quarterControl = 1;
> + nibControl = 0;
> + break;
> + case 3:
> + quarterControl = 1;
> + nibControl = 1;
> + break;
> + default:
> + NOT_IMPLEMENTED;
> + }
> + }
> };
>
> /*! This is a book-keeping structure used to encode both virtual and physical
> @@ -202,6 +224,7 @@ namespace gbe
> int32_t d;
> uint32_t ud;
> uint16_t reg;
> + int64_t i64;
> } value;
>
> uint32_t nr:8; //!< Just for some physical registers (acc, null)
> @@ -434,6 +457,12 @@ namespace gbe
> GEN_HORIZONTAL_STRIDE_0);
> }
>
> + static INLINE GenRegister immint64(int64_t i) {
> + GenRegister immediate = imm(GEN_TYPE_L);
> + immediate.value.i64 = i;
> + return immediate;
> + }
> +
> static INLINE GenRegister immdf(double df) {
> GenRegister immediate = imm(GEN_TYPE_DF);
> immediate.value.df = df;
> --
> 1.8.1.2
>
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