[Beignet] [PATCH v2 1/2] support 64bit-integer selection operator "?:"

[Homer Hsing]

v2: reuse MOV to move 64bit integer. not add MOV_INT64 instruction.

Signed-off-by: Homer Hsing <homer.xing at intel.com>
---
 backend/src/backend/gen_context.cpp        | 19 +++++++++++++++++++
 backend/src/backend/gen_encoder.cpp        | 12 ++++++++++++
 backend/src/backend/gen_insn_selection.cpp |  6 +++++-
 backend/src/backend/gen_insn_selection.hxx |  1 +
 4 files changed, 37 insertions(+), 1 deletion(-)

diff --git a/backend/src/backend/gen_context.cpp b/backend/src/backend/gen_context.cpp
index ec73459..027dbac 100644
--- a/backend/src/backend/gen_context.cpp
+++ b/backend/src/backend/gen_context.cpp
@@ -159,6 +159,25 @@ namespace gbe
       case SEL_OP_LOAD_DF_IMM: p->LOAD_DF_IMM(dst, src1, src0.value.df); break;
       case SEL_OP_MOV_DF: p->MOV_DF(dst, src0, src1); break;
       case SEL_OP_SEL:  p->SEL(dst, src0, src1); break;
+      case SEL_OP_SEL_INT64:
+        {
+          GenRegister xdst = GenRegister::retype(dst, GEN_TYPE_UL),
+                      xsrc0 = GenRegister::retype(src0, GEN_TYPE_UL),
+                      xsrc1 = GenRegister::retype(src1, GEN_TYPE_UL);
+          int execWidth = p->curr.execWidth;
+          p->push();
+          p->curr.execWidth = 8;
+          for (int nib = 0; nib < execWidth / 4; nib ++) {
+            p->curr.chooseNib(nib);
+            p->SEL(xdst.bottom_half(), xsrc0.bottom_half(), xsrc1.bottom_half());
+            p->SEL(xdst.top_half(), xsrc0.top_half(), xsrc1.top_half());
+            xdst = GenRegister::suboffset(xdst, 4);
+            xsrc0 = GenRegister::suboffset(xsrc0, 4);
+            xsrc1 = GenRegister::suboffset(xsrc1, 4);
+          }
+          p->pop();
+        }
+        break;
       case SEL_OP_AND:  p->AND(dst, src0, src1); break;
       case SEL_OP_OR:   p->OR (dst, src0, src1);  break;
       case SEL_OP_XOR:  p->XOR(dst, src0, src1); break;
diff --git a/backend/src/backend/gen_encoder.cpp b/backend/src/backend/gen_encoder.cpp
index 3793d8b..b73bdb9 100644
--- a/backend/src/backend/gen_encoder.cpp
+++ b/backend/src/backend/gen_encoder.cpp
@@ -614,6 +614,18 @@ namespace gbe
   INLINE void alu1(GenEncoder *p, uint32_t opcode, GenRegister dst, GenRegister src) {
      if (dst.isdf() && src.isdf()) {
        handleDouble(p, opcode, dst, src);
+     } else if (dst.isint64() && src.isint64()) { // handle int64
+       int execWidth = p->curr.execWidth;
+       p->push();
+       p->curr.execWidth = 8;
+       for (int nib = 0; nib < execWidth / 4; nib ++) {
+         p->curr.chooseNib(nib);
+         p->MOV(dst.bottom_half(), src.bottom_half());
+         p->MOV(dst.top_half(), src.top_half());
+         dst = GenRegister::suboffset(dst, 4);
+         src = GenRegister::suboffset(src, 4);
+       }
+       p->pop();
      } else if (needToSplitAlu1(p, dst, src) == false) {
        GenInstruction *insn = p->next(opcode);
        p->setHeader(insn);
diff --git a/backend/src/backend/gen_insn_selection.cpp b/backend/src/backend/gen_insn_selection.cpp
index 7e9402d..2a9c846 100644
--- a/backend/src/backend/gen_insn_selection.cpp
+++ b/backend/src/backend/gen_insn_selection.cpp
@@ -419,6 +419,7 @@ namespace gbe
     ALU1(RNDZ)
     ALU1(RNDE)
     ALU2(SEL)
+    ALU2(SEL_INT64)
     ALU1(NOT)
     ALU2(AND)
     ALU2(OR)
@@ -2247,7 +2248,10 @@ namespace gbe
         sel.curr.physicalFlag = 0;
         sel.curr.flagIndex = uint16_t(pred);
         sel.curr.noMask = 0;
-        sel.SEL(tmp, src0, src1);
+        if(type == ir::TYPE_S64 || type == ir::TYPE_U64)
+          sel.SEL_INT64(tmp, src0, src1);
+        else
+          sel.SEL(tmp, src0, src1);
       sel.pop();
 
       // Update the destination register properly now
diff --git a/backend/src/backend/gen_insn_selection.hxx b/backend/src/backend/gen_insn_selection.hxx
index 7664c8f..c510a1c 100644
--- a/backend/src/backend/gen_insn_selection.hxx
+++ b/backend/src/backend/gen_insn_selection.hxx
@@ -11,6 +11,7 @@ DECL_SELECTION_IR(RNDD, UnaryInstruction)
 DECL_SELECTION_IR(RNDU, UnaryInstruction)
 DECL_SELECTION_IR(FRC, UnaryInstruction)
 DECL_SELECTION_IR(SEL, BinaryInstruction)
+DECL_SELECTION_IR(SEL_INT64, BinaryInstruction)
 DECL_SELECTION_IR(AND, BinaryInstruction)
 DECL_SELECTION_IR(OR, BinaryInstruction)
 DECL_SELECTION_IR(XOR, BinaryInstruction)
-- 
1.8.1.2