[Beignet] [PATCH] GBE: set temporary address register for read64 to U64.

[Zhigang Gong]

Ping for comments.

On Mon, Aug 12, 2013 at 03:53:43PM +0800, Zhigang Gong wrote:
> Actually, we really use it as two DWORD rather than U64. But if
> we don't set it to U64, in post scheduler, it doesn't know this
> is a QWORD register and may cause incorrect scheduling.
> 
> We can easily trigger this bug when run compiler_vector_double16_load_store
> with SIMD8 mode. This patch can fix the bug.
> 
> Signed-off-by: Zhigang Gong <zhigang.gong at linux.intel.com>
> ---
>  backend/src/backend/gen_insn_selection.cpp |    2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/backend/src/backend/gen_insn_selection.cpp b/backend/src/backend/gen_insn_selection.cpp
> index 72f6629..9f9cdf6 100644
> --- a/backend/src/backend/gen_insn_selection.cpp
> +++ b/backend/src/backend/gen_insn_selection.cpp
> @@ -1991,7 +1991,7 @@ namespace gbe
>          dst[dstID] = sel.selReg(sel.reg(FAMILY_DWORD));
>        for ( uint32_t valueID = 0; valueID < valueNum; ++dstID, ++valueID)
>          dst[dstID] = sel.selReg(insn.getValue(valueID));
> -      sel.READ64(addr, sel.selReg(sel.reg(FAMILY_QWORD)), dst, valueNum + tmpRegNum, valueNum, bti);
> +      sel.READ64(addr, sel.selReg(sel.reg(FAMILY_QWORD), ir::TYPE_U64), dst, valueNum + tmpRegNum, valueNum, bti);
>      }
>  
>      void emitByteGather(Selection::Opaque &sel,
> -- 
> 1.7.9.5
> 
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