[Beignet] [PATCH] Add bool move imm support.

[Zhigang Gong]

That's will be ok. One case hit this code path and can get expected behaviour, that will be good enough.

On Tue, Aug 13, 2013 at 08:39:08AM +0000, Yang, Rong R wrote:
> Hi, Zhigang,
> 
>   It is hard to construct a test to verify this patch's correctness, I only construct a test case that will assert without this patch.
> 
> -----Original Message-----
> From: Zhigang Gong [mailto:zhigang.gong at linux.intel.com] 
> Sent: Tuesday, August 13, 2013 3:05 PM
> To: Yang, Rong R
> Cc: beignet at lists.freedesktop.org
> Subject: Re: [Beignet] [PATCH] Add bool move imm support.
> 
> Hi Rong,
> 
> could you add a simple case to cover for this code path?
> 
> On Tue, Aug 13, 2013 at 03:06:30PM +0800, Yang Rong wrote:
> > 
> > Signed-off-by: Yang Rong <rong.r.yang at intel.com>
> > ---
> >  backend/src/backend/gen_insn_selection.cpp |   17 +++++++++++++++++
> >  backend/src/ir/instruction.cpp             |    3 ++-
> >  2 files changed, 19 insertions(+), 1 deletion(-)
> > 
> > diff --git a/backend/src/backend/gen_insn_selection.cpp 
> > b/backend/src/backend/gen_insn_selection.cpp
> > index 46da37f..f3122c1 100644
> > --- a/backend/src/backend/gen_insn_selection.cpp
> > +++ b/backend/src/backend/gen_insn_selection.cpp
> > @@ -1893,15 +1893,32 @@ namespace gbe
> >        const Type type = insn.getType();
> >        const Immediate imm = insn.getImmediate();
> >        const GenRegister dst = sel.selReg(insn.getDst(0), type);
> > +      GenRegister flagReg;
> >  
> >        sel.push();
> >        if (sel.isScalarOrBool(insn.getDst(0)) == true) {
> >          sel.curr.execWidth = 1;
> > +        if(type == TYPE_BOOL) {
> > +          if(imm.data.b) {
> > +            if(sel.curr.predicate == GEN_PREDICATE_NONE)
> > +              flagReg = GenRegister::immuw(0xffff);
> > +            else {
> > +              if(sel.curr.physicalFlag)
> > +                flagReg = GenRegister::flag(sel.curr.flag, sel.curr.subFlag);
> > +              else
> > +                flagReg = sel.selReg(Register(sel.curr.flagIndex), TYPE_U16);
> > +            }
> > +          } else
> > +            flagReg = GenRegister::immuw(0x0);
> > +        }
> >          sel.curr.predicate = GEN_PREDICATE_NONE;
> >          sel.curr.noMask = 1;
> >        }
> >  
> >        switch (type) {
> > +        case TYPE_BOOL:
> > +          sel.MOV(dst, flagReg);
> > +        break;
> >          case TYPE_U32:
> >          case TYPE_S32:
> >          case TYPE_FLOAT:
> > diff --git a/backend/src/ir/instruction.cpp 
> > b/backend/src/ir/instruction.cpp index 45095db..3b5ff08 100644
> > --- a/backend/src/ir/instruction.cpp
> > +++ b/backend/src/ir/instruction.cpp
> > @@ -861,7 +861,8 @@ namespace ir {
> >          return false;
> >        if (UNLIKELY(checkRegisterData(family, dst[0], fn, whyNot) == false))
> >          return false;
> > -      CHECK_TYPE(this->type, allButBool);
> > +      //Support all type IMM, disable check
> > +      //CHECK_TYPE(this->type, allButBool);
> >        return true;
> >      }
> >  
> > --
> > 1.7.10.4
> > 
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