[Beignet] [PATCH] enable signed 64-bit version of "abs_diff"

[Zhigang Gong]

LGTM, pushed, thanks.

On Mon, Aug 19, 2013 at 02:55:29PM +0800, Homer Hsing wrote:
> fixed operand type in IR instruction "move".
> used one less flag register in 64-bit integer comparing.
> 
> Signed-off-by: Homer Hsing <homer.xing at intel.com>
> ---
>  backend/src/backend/gen_context.cpp        | 22 +++++++++++-----------
>  backend/src/backend/gen_insn_selection.cpp |  9 ++++++---
>  backend/src/ocl_stdlib.tmpl.h              |  4 +++-
>  3 files changed, 20 insertions(+), 15 deletions(-)
> 
> diff --git a/backend/src/backend/gen_context.cpp b/backend/src/backend/gen_context.cpp
> index 8d4bc7a..e8b5c41 100644
> --- a/backend/src/backend/gen_context.cpp
> +++ b/backend/src/backend/gen_context.cpp
> @@ -535,10 +535,11 @@ namespace gbe
>      int flag = p->curr.flag, subFlag = p->curr.subFlag;
>      GenRegister f1 = GenRegister::retype(tmp2, GEN_TYPE_UW),
>                  f2 = GenRegister::suboffset(f1, 1),
> -                f3 = GenRegister::suboffset(f1, 2);
> +                f3 = GenRegister::suboffset(f1, 2),
> +                f4 = GenRegister::suboffset(f1, 3);
>      p->push();
>      p->curr.predicate = GEN_PREDICATE_NONE;
> -    p->curr.flag = 0, p->curr.subFlag = 1;
> +    saveFlag(f4, flag, subFlag);
>      loadTopHalf(tmp0, src0);
>      loadTopHalf(tmp1, src1);
>      switch(insn.extra.function) {
> @@ -554,14 +555,14 @@ namespace gbe
>              cmpTopHalf = GEN_CONDITIONAL_G;
>            p->CMP(cmpTopHalf, tmp0, tmp1);
>          }
> -        saveFlag(f1, 0, 1);
> +        saveFlag(f1, flag, subFlag);
>          p->CMP(GEN_CONDITIONAL_EQ, tmp0, tmp1);
> -        saveFlag(f2, 0, 1);
> +        saveFlag(f2, flag, subFlag);
>          tmp0.type = tmp1.type = GEN_TYPE_UD;
>          loadBottomHalf(tmp0, src0);
>          loadBottomHalf(tmp1, src1);
>          p->CMP(insn.extra.function, tmp0, tmp1);
> -        saveFlag(f3, 0, 1);
> +        saveFlag(f3, flag, subFlag);
>          p->push();
>          p->curr.execWidth = 1;
>          p->AND(f2, f2, f3);
> @@ -570,12 +571,12 @@ namespace gbe
>          break;
>        case GEN_CONDITIONAL_EQ:
>          p->CMP(GEN_CONDITIONAL_EQ, tmp0, tmp1);
> -        saveFlag(f1, 0, 1);
> +        saveFlag(f1, flag, subFlag);
>          tmp0.type = tmp1.type = GEN_TYPE_UD;
>          loadBottomHalf(tmp0, src0);
>          loadBottomHalf(tmp1, src1);
>          p->CMP(GEN_CONDITIONAL_EQ, tmp0, tmp1);
> -        saveFlag(f2, 0, 1);
> +        saveFlag(f2, flag, subFlag);
>          p->push();
>          p->curr.execWidth = 1;
>          p->AND(f1, f1, f2);
> @@ -583,12 +584,12 @@ namespace gbe
>          break;
>        case GEN_CONDITIONAL_NEQ:
>          p->CMP(GEN_CONDITIONAL_NEQ, tmp0, tmp1);
> -        saveFlag(f1, 0, 1);
> +        saveFlag(f1, flag, subFlag);
>          tmp0.type = tmp1.type = GEN_TYPE_UD;
>          loadBottomHalf(tmp0, src0);
>          loadBottomHalf(tmp1, src1);
>          p->CMP(GEN_CONDITIONAL_NEQ, tmp0, tmp1);
> -        saveFlag(f2, 0, 1);
> +        saveFlag(f2, flag, subFlag);
>          p->push();
>          p->curr.execWidth = 1;
>          p->OR(f1, f1, f2);
> @@ -597,9 +598,8 @@ namespace gbe
>        default:
>          NOT_IMPLEMENTED;
>      }
> -    saveFlag(f2, flag, subFlag);
>      p->curr.execWidth = 1;
> -    p->AND(f1, f1, f2);
> +    p->AND(f1, f1, f4);
>      p->MOV(GenRegister::flag(flag, subFlag), f1);
>      p->pop();
>    }
> diff --git a/backend/src/backend/gen_insn_selection.cpp b/backend/src/backend/gen_insn_selection.cpp
> index 90ffd7c..55db48e 100644
> --- a/backend/src/backend/gen_insn_selection.cpp
> +++ b/backend/src/backend/gen_insn_selection.cpp
> @@ -1384,7 +1384,9 @@ namespace gbe
>    /*! Unary instruction patterns */
>    DECL_PATTERN(UnaryInstruction)
>    {
> -    static ir::Type getType(const ir::Opcode opcode) {
> +    static ir::Type getType(const ir::Opcode opcode, const ir::Type insnType) {
> +      if (insnType == ir::TYPE_S64 || insnType == ir::TYPE_U64)
> +        return insnType;
>        if (opcode == ir::OP_FBH || opcode == ir::OP_FBL)
>          return ir::TYPE_U32;
>        return ir::TYPE_FLOAT;
> @@ -1392,8 +1394,9 @@ namespace gbe
>  
>      INLINE bool emitOne(Selection::Opaque &sel, const ir::UnaryInstruction &insn) const {
>        const ir::Opcode opcode = insn.getOpcode();
> -      const GenRegister dst = sel.selReg(insn.getDst(0), getType(opcode));
> -      const GenRegister src = sel.selReg(insn.getSrc(0), getType(opcode));
> +      const ir::Type insnType = insn.getType();
> +      const GenRegister dst = sel.selReg(insn.getDst(0), getType(opcode, insnType));
> +      const GenRegister src = sel.selReg(insn.getSrc(0), getType(opcode, insnType));
>        switch (opcode) {
>          case ir::OP_ABS:
>            if (insn.getType() == ir::TYPE_S32) {
> diff --git a/backend/src/ocl_stdlib.tmpl.h b/backend/src/ocl_stdlib.tmpl.h
> index 59c0f6b..c428fac 100644
> --- a/backend/src/ocl_stdlib.tmpl.h
> +++ b/backend/src/ocl_stdlib.tmpl.h
> @@ -508,7 +508,9 @@ INLINE_OVERLOADABLE uint abs_diff (int x, int y) {
>  }
>  
>  INLINE_OVERLOADABLE ulong abs_diff (long x, long y) {
> -  return 0;
> +  if ((x >= 0 && y >= 0) || (x <= 0 && y <= 0))
> +    return abs(x - y);
> +  return abs(x) + abs(y);
>  }
>  INLINE_OVERLOADABLE ulong abs_diff (ulong x, ulong y) {
>    return y > x ? (y - x) : (x - y);
> -- 
> 1.8.1.2
> 
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