[Beignet] [PATCH 1/2] padding enough temporary registers in 64-bit IO

[Homer Hsing]

Temporary registers are required in 64-bit data type IO.

Previously padded QWORD register was allocated as DWORD.
Here split QWORD into DWORD regs.

In 64-bit reading, temporary registers is next to the dest reg.

In 64-bit writing, temporary registers is 2*GEN_REG_SIZE
away from the message reg.

Signed-off-by: Homer Hsing <homer.xing at intel.com>
---
 backend/src/backend/gen_encoder.cpp        |  6 +++---
 backend/src/backend/gen_insn_selection.cpp | 18 ++++++++++++------
 2 files changed, 15 insertions(+), 9 deletions(-)

diff --git a/backend/src/backend/gen_encoder.cpp b/backend/src/backend/gen_encoder.cpp
index f84c6dd..ee58a7d 100644
--- a/backend/src/backend/gen_encoder.cpp
+++ b/backend/src/backend/gen_encoder.cpp
@@ -367,10 +367,10 @@ namespace gbe
 
   void GenEncoder::READ_FLOAT64(GenRegister dst, GenRegister src, uint32_t bti, uint32_t elemNum) {
     int w = curr.execWidth;
-    dst = GenRegister::h2(dst);
     dst.type = GEN_TYPE_UD;
     src.type = GEN_TYPE_UD;
-    GenRegister r = GenRegister::retype(GenRegister::suboffset(src, w*2), GEN_TYPE_UD);
+    GenRegister r = GenRegister::retype(GenRegister::suboffset(dst, w*2), GEN_TYPE_UD);
+    dst = GenRegister::h2(dst);
     GenRegister imm4 = GenRegister::immud(4);
     GenInstruction *insn;
     insn = next(GEN_OPCODE_SEND);
@@ -410,7 +410,7 @@ namespace gbe
 
   void GenEncoder::WRITE_FLOAT64(GenRegister msg, uint32_t bti, uint32_t elemNum) {
     int w = curr.execWidth;
-    GenRegister r = GenRegister::retype(GenRegister::suboffset(msg, w*3), GEN_TYPE_UD);
+    GenRegister r = GenRegister::retype(GenRegister::suboffset(msg, w*4), GEN_TYPE_UD);
     r.type = GEN_TYPE_UD;
     GenRegister hdr = GenRegister::h2(r);
     GenRegister src = GenRegister::ud16grf(msg.nr + w / 8, 0);
diff --git a/backend/src/backend/gen_insn_selection.cpp b/backend/src/backend/gen_insn_selection.cpp
index d4be8bf..e3470ea 100644
--- a/backend/src/backend/gen_insn_selection.cpp
+++ b/backend/src/backend/gen_insn_selection.cpp
@@ -1874,9 +1874,12 @@ namespace gbe
       vector<GenRegister> dst(valueNum);
       for (uint32_t dstID = 0; dstID < valueNum; ++dstID)
         dst[dstID] = GenRegister::retype(sel.selReg(insn.getValue(dstID)), GEN_TYPE_F);
-      dst.push_back(sel.selReg(sel.reg(FAMILY_QWORD)));
-      if (sel.ctx.getSimdWidth() == 16)
-        dst.push_back(sel.selReg(sel.reg(FAMILY_QWORD)));
+      dst.push_back(sel.selReg(sel.reg(FAMILY_DWORD)));
+      dst.push_back(sel.selReg(sel.reg(FAMILY_DWORD)));
+      if (sel.ctx.getSimdWidth() == 16) {
+        dst.push_back(sel.selReg(sel.reg(FAMILY_DWORD)));
+        dst.push_back(sel.selReg(sel.reg(FAMILY_DWORD)));
+      }
       sel.READ_FLOAT64(addr, dst.data(), dst.size(), bti);
     }
 
@@ -1976,9 +1979,12 @@ namespace gbe
       addr = GenRegister::retype(sel.selReg(insn.getSrc(addrID)), GEN_TYPE_F);
       for (uint32_t valueID = 0; valueID < valueNum; ++valueID)
         value[valueID] = GenRegister::retype(sel.selReg(insn.getValue(valueID)), GEN_TYPE_F);
-      value.push_back(sel.selReg(sel.reg(FAMILY_QWORD)));
-      if (sel.ctx.getSimdWidth() == 16)
-        value.push_back(sel.selReg(sel.reg(FAMILY_QWORD)));
+      value.push_back(sel.selReg(sel.reg(FAMILY_DWORD)));
+      value.push_back(sel.selReg(sel.reg(FAMILY_DWORD)));
+      if (sel.ctx.getSimdWidth() == 16) {
+        value.push_back(sel.selReg(sel.reg(FAMILY_DWORD)));
+        value.push_back(sel.selReg(sel.reg(FAMILY_DWORD)));
+      }
       sel.WRITE_FLOAT64(addr, value.data(), value.size(), bti);
     }
 
-- 
1.8.1.2