[Beignet] [PATCH] Rename CBMove to IndirectMove

[Yang Rong]

Signed-off-by: Yang Rong <rong.r.yang at intel.com>
---
 backend/src/backend/gen_context.cpp                |    2 +-
 backend/src/backend/gen_context.hpp                |    2 +-
 .../src/backend/gen_insn_gen7_schedule_info.hxx    |    2 +-
 backend/src/backend/gen_insn_selection.cpp         |   12 ++++++------
 backend/src/backend/gen_insn_selection.hxx         |    2 +-
 5 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/backend/src/backend/gen_context.cpp b/backend/src/backend/gen_context.cpp
index 4a16cae..38be4f6 100644
--- a/backend/src/backend/gen_context.cpp
+++ b/backend/src/backend/gen_context.cpp
@@ -212,7 +212,7 @@ namespace gbe
     }
   }
 
-  void GenContext::emitCBMoveInstruction(const SelectionInstruction &insn) {
+  void GenContext::emitIndirectMoveInstruction(const SelectionInstruction &insn) {
     const GenRegister src = GenRegister::unpacked_uw(ra->genReg(insn.src(0)).nr, 0);
     const GenRegister dst = ra->genReg(insn.dst(0));
     const GenRegister a0 = GenRegister::addr8(0);
diff --git a/backend/src/backend/gen_context.hpp b/backend/src/backend/gen_context.hpp
index 33258f8..fccd0c6 100644
--- a/backend/src/backend/gen_context.hpp
+++ b/backend/src/backend/gen_context.hpp
@@ -80,7 +80,7 @@ namespace gbe
     void emitTernaryInstruction(const SelectionInstruction &insn);
     void emitCompareInstruction(const SelectionInstruction &insn);
     void emitJumpInstruction(const SelectionInstruction &insn);
-    void emitCBMoveInstruction(const SelectionInstruction &insn);
+    void emitIndirectMoveInstruction(const SelectionInstruction &insn);
     void emitEotInstruction(const SelectionInstruction &insn);
     void emitNoOpInstruction(const SelectionInstruction &insn);
     void emitWaitInstruction(const SelectionInstruction &insn);
diff --git a/backend/src/backend/gen_insn_gen7_schedule_info.hxx b/backend/src/backend/gen_insn_gen7_schedule_info.hxx
index ce8769f..113fa71 100644
--- a/backend/src/backend/gen_insn_gen7_schedule_info.hxx
+++ b/backend/src/backend/gen_insn_gen7_schedule_info.hxx
@@ -5,7 +5,7 @@ DECL_GEN7_SCHEDULE(Binary,          20,        4,        2)
 DECL_GEN7_SCHEDULE(Ternary,         20,        4,        2)
 DECL_GEN7_SCHEDULE(Compare,         20,        4,        2)
 DECL_GEN7_SCHEDULE(Jump,            14,        1,        1)
-DECL_GEN7_SCHEDULE(CBMove,          20,        2,        2)
+DECL_GEN7_SCHEDULE(IndirectMove,    20,        2,        2)
 DECL_GEN7_SCHEDULE(Eot,             20,        1,        1)
 DECL_GEN7_SCHEDULE(NoOp,            20,        2,        2)
 DECL_GEN7_SCHEDULE(Wait,            20,        2,        2)
diff --git a/backend/src/backend/gen_insn_selection.cpp b/backend/src/backend/gen_insn_selection.cpp
index 2bd9aca..c6527be 100644
--- a/backend/src/backend/gen_insn_selection.cpp
+++ b/backend/src/backend/gen_insn_selection.cpp
@@ -440,7 +440,7 @@ namespace gbe
     /*! Select instruction with embedded comparison */
     void SEL_CMP(uint32_t conditional, Reg dst, Reg src0, Reg src1);
     /* Constant buffer move instruction */
-    void CB_MOVE(Reg dst, Reg src);
+    void INDIRECT_MOVE(Reg dst, Reg src);
     /*! EOT is used to finish GPGPU threads */
     void EOT(void);
     /*! No-op */
@@ -700,8 +700,8 @@ namespace gbe
     insn->src(1) = src1;
     insn->extra.function = conditional;
   }
-  void Selection::Opaque::CB_MOVE(Reg dst, Reg src) {
-    SelectionInstruction *insn = this->appendInsn(SEL_OP_CB_MOVE, 1, 1);
+  void Selection::Opaque::INDIRECT_MOVE(Reg dst, Reg src) {
+    SelectionInstruction *insn = this->appendInsn(SEL_OP_INDIRECT_MOVE, 1, 1);
     insn->dst(0) = dst;
     insn->src(0) = src;
   }
@@ -1661,7 +1661,7 @@ namespace gbe
         sel.MOV(GenRegister::retype(value, GEN_TYPE_UB), GenRegister::unpacked_ub(dst));
     }
 
-    void emitCBMove(Selection::Opaque &sel,
+    void emitIndirectMove(Selection::Opaque &sel,
                          const ir::LoadInstruction &insn,
                          GenRegister address) const
     {
@@ -1670,7 +1670,7 @@ namespace gbe
 
       const GenRegister dst = sel.selReg(insn.getValue(0), insn.getValueType());
       const GenRegister src = address;
-      sel.CB_MOVE(dst, src);
+      sel.INDIRECT_MOVE(dst, src);
     }
 
     INLINE bool emitOne(Selection::Opaque &sel, const ir::LoadInstruction &insn) const {
@@ -1683,7 +1683,7 @@ namespace gbe
                  insn.getAddressSpace() == MEM_LOCAL);
       GBE_ASSERT(sel.ctx.isScalarReg(insn.getValue(0)) == false);
       if (insn.getAddressSpace() == MEM_CONSTANT)
-        this->emitCBMove(sel, insn, address);
+        this->emitIndirectMove(sel, insn, address);
       else if (insn.isAligned() == true)
         this->emitUntypedRead(sel, insn, address, space == MEM_LOCAL ? 0xfe : 0x00);
       else {
diff --git a/backend/src/backend/gen_insn_selection.hxx b/backend/src/backend/gen_insn_selection.hxx
index f89ad4c..4c6a3de 100644
--- a/backend/src/backend/gen_insn_selection.hxx
+++ b/backend/src/backend/gen_insn_selection.hxx
@@ -24,7 +24,7 @@ DECL_SELECTION_IR(SEL_CMP, CompareInstruction)
 DECL_SELECTION_IR(MAD, TernaryInstruction)
 DECL_SELECTION_IR(JMPI, JumpInstruction)
 DECL_SELECTION_IR(EOT, EotInstruction)
-DECL_SELECTION_IR(CB_MOVE, CBMoveInstruction)
+DECL_SELECTION_IR(INDIRECT_MOVE, IndirectMoveInstruction)
 DECL_SELECTION_IR(NOP, NoOpInstruction)
 DECL_SELECTION_IR(WAIT, WaitInstruction)
 DECL_SELECTION_IR(MATH, MathInstruction)
-- 
1.7.9.5