[Beignet] [PATCH] fix ASR operator for 64bit integer

[Yang, Rong R]

LGTM, thanks.

-----Original Message-----
From: beignet-bounces at lists.freedesktop.org [mailto:beignet-bounces at lists.freedesktop.org] On Behalf Of Homer Hsing
Sent: Monday, November 04, 2013 10:14 AM
To: beignet at lists.freedesktop.org
Subject: [Beignet] [PATCH] fix ASR operator for 64bit integer

if operand is positive, then pad zero at high 32 bit.

Signed-off-by: Homer Hsing <homer.xing at intel.com>
---
 backend/src/backend/gen_context.cpp | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/backend/src/backend/gen_context.cpp b/backend/src/backend/gen_context.cpp
index 43b3bc7..6007904 100644
--- a/backend/src/backend/gen_context.cpp
+++ b/backend/src/backend/gen_context.cpp
@@ -811,12 +811,13 @@ namespace gbe
         p->SEL(d, d, e);
         p->curr.predicate = GEN_PREDICATE_NONE;
         p->AND(a, a, GenRegister::immud(32));
+        p->ASR(f, f, GenRegister::immd(31));
         p->MOV(flagReg, GenRegister::immuw(0xFFFF));
         p->curr.predicate = GEN_PREDICATE_NORMAL;
         p->curr.useFlag(flagReg.flag_nr(), flagReg.flag_subnr());
         p->CMP(GEN_CONDITIONAL_Z, a, zero);
         p->SEL(d, d, c);
-        p->SEL(c, c, GenRegister::immd(-1));
+        p->SEL(c, c, f);
         p->pop();
         storeBottomHalf(dest, d);
         storeTopHalf(dest, c);
-- 
1.8.3.2

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