[Beignet] [Patch V3] Add FCmpInst ord support.

[Zhigang Gong]

LGTM, pushed, thanks.

On Fri, Nov 15, 2013 at 01:45:53PM +0800, Yang Rong wrote:
> Because gen do not support isorder direct, use (src0 == src0) && (src1 == src1).
> BTW: can't use !unordered.
> 
> v2: Refine, don't need AND.
> v3: Do not change getGenCompare function.
> 
> Signed-off-by: Yang Rong <rong.r.yang at intel.com>
> ---
>  backend/src/backend/gen_insn_selection.cpp | 9 ++++++---
>  backend/src/ir/instruction.cpp             | 1 +
>  backend/src/ir/instruction.hpp             | 2 ++
>  backend/src/ir/instruction.hxx             | 1 +
>  backend/src/llvm/llvm_gen_backend.cpp      | 1 +
>  5 files changed, 11 insertions(+), 3 deletions(-)
> 
> diff --git a/backend/src/backend/gen_insn_selection.cpp b/backend/src/backend/gen_insn_selection.cpp
> index 5a6b9fd..bcdc308 100644
> --- a/backend/src/backend/gen_insn_selection.cpp
> +++ b/backend/src/backend/gen_insn_selection.cpp
> @@ -1955,6 +1955,7 @@ namespace gbe
>        // OK, we merge the instructions
>        const ir::CompareInstruction &cmpInsn = cast<CompareInstruction>(cmp->insn);
>        const ir::Opcode opcode = cmpInsn.getOpcode();
> +      if(opcode == OP_ORD) return false;
>        const uint32_t genCmp = getGenCompare(opcode);
>  
>        // Like for regular selects, we need a temporary since we cannot predicate
> @@ -2504,7 +2505,6 @@ namespace gbe
>        const ir::CompareInstruction &insn = cast<CompareInstruction>(dag.insn);
>        const Opcode opcode = insn.getOpcode();
>        const Type type = insn.getType();
> -      const uint32_t genCmp = getGenCompare(opcode);
>        const Register dst = insn.getDst(0);
>  
>        // Limit the compare to the active lanes. Use the same compare as for f0.0
> @@ -2542,9 +2542,12 @@ namespace gbe
>            GenRegister tmp[3];
>            for(int i=0; i<3; i++)
>              tmp[i] = sel.selReg(sel.reg(FAMILY_DWORD));
> -          sel.I64CMP(genCmp, src0, src1, tmp);
> +          sel.I64CMP(getGenCompare(opcode), src0, src1, tmp);
> +        } else if(opcode == OP_ORD) {
> +          sel.CMP(GEN_CONDITIONAL_EQ, src0, src0);
> +          sel.CMP(GEN_CONDITIONAL_EQ, src1, src1);
>          } else
> -          sel.CMP(genCmp, src0, src1);
> +          sel.CMP(getGenCompare(opcode), src0, src1);
>        sel.pop();
>        return true;
>      }
> diff --git a/backend/src/ir/instruction.cpp b/backend/src/ir/instruction.cpp
> index da20d43..c624d7a 100644
> --- a/backend/src/ir/instruction.cpp
> +++ b/backend/src/ir/instruction.cpp
> @@ -1552,6 +1552,7 @@ DECL_MEM_FN(GetImageInfoInstruction, uint32_t, getInfoType(void), getInfoType())
>    DECL_EMIT_FUNCTION(LT)
>    DECL_EMIT_FUNCTION(GE)
>    DECL_EMIT_FUNCTION(GT)
> +  DECL_EMIT_FUNCTION(ORD)
>  
>  #undef DECL_EMIT_FUNCTION
>  
> diff --git a/backend/src/ir/instruction.hpp b/backend/src/ir/instruction.hpp
> index b1afd42..b7eebc0 100644
> --- a/backend/src/ir/instruction.hpp
> +++ b/backend/src/ir/instruction.hpp
> @@ -634,6 +634,8 @@ namespace ir {
>    Instruction GE(Type type, Register dst, Register src0, Register src1);
>    /*! ge.type dst src0 src1 */
>    Instruction GT(Type type, Register dst, Register src0, Register src1);
> +  /*! ord.type dst src0 src1 */
> +  Instruction ORD(Type type, Register dst, Register src0, Register src1);
>    /*! BITCAST.{dstType <- srcType} dst src */
>    Instruction BITCAST(Type dstType, Type srcType, Tuple dst, Tuple src, uint8_t dstNum, uint8_t srcNum);
>    /*! cvt.{dstType <- srcType} dst src */
> diff --git a/backend/src/ir/instruction.hxx b/backend/src/ir/instruction.hxx
> index 83ecd1d..cf79e09 100644
> --- a/backend/src/ir/instruction.hxx
> +++ b/backend/src/ir/instruction.hxx
> @@ -60,6 +60,7 @@ DECL_INSN(LE, CompareInstruction)
>  DECL_INSN(LT, CompareInstruction)
>  DECL_INSN(GE, CompareInstruction)
>  DECL_INSN(GT, CompareInstruction)
> +DECL_INSN(ORD, CompareInstruction)
>  DECL_INSN(BITCAST, BitCastInstruction)
>  DECL_INSN(CVT, ConvertInstruction)
>  DECL_INSN(SAT_CVT, ConvertInstruction)
> diff --git a/backend/src/llvm/llvm_gen_backend.cpp b/backend/src/llvm/llvm_gen_backend.cpp
> index 23e5442..688c2b2 100644
> --- a/backend/src/llvm/llvm_gen_backend.cpp
> +++ b/backend/src/llvm/llvm_gen_backend.cpp
> @@ -1596,6 +1596,7 @@ namespace gbe
>        case ICmpInst::FCMP_ULT: ctx.LT(type, dst, src0, src1); break;
>        case ICmpInst::FCMP_OGT:
>        case ICmpInst::FCMP_UGT: ctx.GT(type, dst, src0, src1); break;
> +      case ICmpInst::FCMP_ORD: ctx.ORD(type, dst, src0, src0); break;
>        default: NOT_SUPPORTED;
>      }
>    }
> -- 
> 1.8.1.2
> 
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