[Beignet] [PATCH] Fix B/UB compare fail.

[Zhigang Gong]

LGTM, will push latter. Thanks.

On Thu, Nov 28, 2013 at 04:37:22PM +0800, Yang Rong wrote:
> Because B/UB is treated as W/UW, so can't set src1's type when dismatch.
> Set the correct type before getRegisterFromImmediate.
> 
> Signed-off-by: Yang Rong <rong.r.yang at intel.com>
> ---
>  backend/src/backend/gen_insn_selection.cpp | 7 ++++---
>  1 file changed, 4 insertions(+), 3 deletions(-)
> 
> diff --git a/backend/src/backend/gen_insn_selection.cpp b/backend/src/backend/gen_insn_selection.cpp
> index 3661c2b..f532158 100644
> --- a/backend/src/backend/gen_insn_selection.cpp
> +++ b/backend/src/backend/gen_insn_selection.cpp
> @@ -2529,9 +2529,10 @@ namespace gbe
>        if (OCL_OPTIMIZE_IMMEDIATE && dag1 != NULL && dag1->insn.getOpcode() == OP_LOADI && canGetRegisterFromImmediate(dag1->insn)) {
>          const auto &childInsn = cast<LoadImmInstruction>(dag1->insn);
>          src0 = sel.selReg(insn.getSrc(0), type);
> -        src1 = getRegisterFromImmediate(childInsn.getImmediate());
> -        if(src1.type != src0.type)
> -          src1 = GenRegister::retype(src1, src0.type);
> +        Immediate imm = childInsn.getImmediate();
> +        if(imm.type != type)
> +          imm.type = type;
> +        src1 = getRegisterFromImmediate(imm);
>          if (dag0) dag0->isRoot = 1;
>        } else {
>          src0 = sel.selReg(insn.getSrc(0), type);
> -- 
> 1.8.1.2
> 
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