[Beignet] [PATCH 1/3] GBE: Enable DWord scatter gather message for constant cache read.
Ruiling Song
ruiling.song at intel.com
Tue Sep 3 00:42:35 PDT 2013
Signed-off-by: Ruiling Song <ruiling.song at intel.com>
---
backend/src/backend/gen/gen_mesa_disasm.c | 5 +++
backend/src/backend/gen_context.cpp | 7 +++
backend/src/backend/gen_context.hpp | 1 +
backend/src/backend/gen_defs.hpp | 19 ++++++++
backend/src/backend/gen_encoder.cpp | 46 +++++++++++++++++++-
backend/src/backend/gen_encoder.hpp | 2 +
.../src/backend/gen_insn_gen7_schedule_info.hxx | 1 +
backend/src/backend/gen_insn_selection.cpp | 10 +++++
backend/src/backend/gen_insn_selection.hxx | 1 +
9 files changed, 91 insertions(+), 1 deletion(-)
diff --git a/backend/src/backend/gen/gen_mesa_disasm.c b/backend/src/backend/gen/gen_mesa_disasm.c
index bfb865a..f911e7c 100644
--- a/backend/src/backend/gen/gen_mesa_disasm.c
+++ b/backend/src/backend/gen/gen_mesa_disasm.c
@@ -1193,6 +1193,11 @@ int gen_disasm (FILE *file, const void *opaque_insn)
data_port_scratch_msg_type[inst->bits3.gen7_scratch_rw.msg_type]);
}
break;
+ case GEN6_SFID_DATAPORT_CONSTANT_CACHE:
+ format (file, " (bti: %d, %s)",
+ inst->bits3.gen7_dword_rw.bti,
+ data_port_data_cache_msg_type[inst->bits3.gen7_dword_rw.msg_type]);
+ break;
case GEN_SFID_MESSAGE_GATEWAY:
format (file, " (subfunc: %s, notify: %d, ackreq: %d)",
gateway_sub_function[inst->bits3.gen7_msg_gw.subfunc],
diff --git a/backend/src/backend/gen_context.cpp b/backend/src/backend/gen_context.cpp
index a029719..763ea5b 100644
--- a/backend/src/backend/gen_context.cpp
+++ b/backend/src/backend/gen_context.cpp
@@ -963,6 +963,13 @@ namespace gbe
p->BYTE_SCATTER(src, bti, elemSize);
}
+ void GenContext::emitDWordGatherInstruction(const SelectionInstruction &insn) {
+ const GenRegister dst = ra->genReg(insn.dst(0));
+ const GenRegister src = ra->genReg(insn.src(0));
+ const uint32_t bti = insn.extra.function;
+ p->DWORD_GATHER(dst, src, bti);
+ }
+
void GenContext::emitSampleInstruction(const SelectionInstruction &insn) {
const GenRegister dst = ra->genReg(insn.dst(0));
const GenRegister msgPayload = GenRegister::retype(ra->genReg(insn.src(0)), GEN_TYPE_F);
diff --git a/backend/src/backend/gen_context.hpp b/backend/src/backend/gen_context.hpp
index f66ec95..14e4550 100644
--- a/backend/src/backend/gen_context.hpp
+++ b/backend/src/backend/gen_context.hpp
@@ -114,6 +114,7 @@ namespace gbe
void emitAtomicInstruction(const SelectionInstruction &insn);
void emitByteGatherInstruction(const SelectionInstruction &insn);
void emitByteScatterInstruction(const SelectionInstruction &insn);
+ void emitDWordGatherInstruction(const SelectionInstruction &insn);
void emitSampleInstruction(const SelectionInstruction &insn);
void emitTypedWriteInstruction(const SelectionInstruction &insn);
void emitSpillRegInstruction(const SelectionInstruction &insn);
diff --git a/backend/src/backend/gen_defs.hpp b/backend/src/backend/gen_defs.hpp
index e3959ff..27ce58c 100644
--- a/backend/src/backend/gen_defs.hpp
+++ b/backend/src/backend/gen_defs.hpp
@@ -343,6 +343,10 @@ enum GenMessageTarget {
#define GEN_BYTE_SCATTER_DWORD 2
#define GEN_BYTE_SCATTER_QWORD 3
+/* dword scattered rw */
+#define GEN_DWORD_SCATTER_8_DWORDS 2
+#define GEN_DWORD_SCATTER_16_DWORDS 3
+
#define GEN_SAMPLER_RETURN_FORMAT_FLOAT32 0
#define GEN_SAMPLER_RETURN_FORMAT_UINT32 2
#define GEN_SAMPLER_RETURN_FORMAT_SINT32 3
@@ -805,6 +809,21 @@ struct GenInstruction
uint32_t end_of_thread:1;
} gen7_oblock_rw;
+ /*! Data port dword scatter / gather */
+ struct {
+ uint32_t bti:8;
+ uint32_t block_size:2;
+ uint32_t ignored0:3;
+ uint32_t invalidate_after_read:1;
+ uint32_t msg_type:4;
+ uint32_t ignored1:1;
+ uint32_t header_present:1;
+ uint32_t response_length:5;
+ uint32_t msg_length:4;
+ uint32_t pad2:2;
+ uint32_t end_of_thread:1;
+ } gen7_dword_rw;
+
/*! Data port typed read / write messages */
struct {
uint32_t bti:8;
diff --git a/backend/src/backend/gen_encoder.cpp b/backend/src/backend/gen_encoder.cpp
index a3d576e..35e2cee 100644
--- a/backend/src/backend/gen_encoder.cpp
+++ b/backend/src/backend/gen_encoder.cpp
@@ -198,7 +198,21 @@ namespace gbe
insn->bits3.gen7_typed_rw.bti = bti;
insn->bits3.gen7_typed_rw.msg_type = msg_type;
}
-
+ static void setDWordScatterMessgae(GenEncoder *p,
+ GenInstruction *insn,
+ uint32_t bti,
+ uint32_t block_size,
+ uint32_t msg_type,
+ uint32_t msg_length,
+ uint32_t response_length)
+ {
+ const GenMessageTarget sfid = GEN6_SFID_DATAPORT_CONSTANT_CACHE;
+ setMessageDescriptor(p, insn, sfid, msg_length, response_length);
+ insn->bits3.gen7_dword_rw.msg_type = msg_type;
+ insn->bits3.gen7_dword_rw.bti = bti;
+ insn->bits3.gen7_dword_rw.block_size = block_size;
+ insn->bits3.gen7_dword_rw.invalidate_after_read = 0;
+ }
//////////////////////////////////////////////////////////////////////////
// Gen Emitter encoding class
//////////////////////////////////////////////////////////////////////////
@@ -519,6 +533,36 @@ namespace gbe
response_length);
}
+ void GenEncoder::DWORD_GATHER(GenRegister dst, GenRegister src, uint32_t bti) {
+ GenInstruction *insn = this->next(GEN_OPCODE_SEND);
+ uint32_t msg_length = 0;
+ uint32_t response_length = 0;
+ uint32_t block_size = 0;
+ if (this->curr.execWidth == 8) {
+ msg_length = 1;
+ response_length = 1;
+ block_size = GEN_DWORD_SCATTER_8_DWORDS;
+ } else if (this->curr.execWidth == 16) {
+ msg_length = 2;
+ response_length = 2;
+ block_size = GEN_DWORD_SCATTER_16_DWORDS;
+ } else
+ NOT_IMPLEMENTED;
+
+ this->setHeader(insn);
+ this->setDst(insn, dst);
+ this->setSrc0(insn, src);
+ this->setSrc1(insn, GenRegister::immud(0));
+ setDWordScatterMessgae(this,
+ insn,
+ bti,
+ block_size,
+ GEN_DWORD_GATHER,
+ msg_length,
+ response_length);
+
+ }
+
void GenEncoder::ATOMIC(GenRegister dst, uint32_t function, GenRegister src, uint32_t bti, uint32_t srcNum) {
GenInstruction *insn = this->next(GEN_OPCODE_SEND);
uint32_t msg_length = 0;
diff --git a/backend/src/backend/gen_encoder.hpp b/backend/src/backend/gen_encoder.hpp
index bbf240c..d90033e 100644
--- a/backend/src/backend/gen_encoder.hpp
+++ b/backend/src/backend/gen_encoder.hpp
@@ -156,6 +156,8 @@ namespace gbe
void BYTE_GATHER(GenRegister dst, GenRegister src, uint32_t bti, uint32_t elemSize);
/*! Byte scatter (for unaligned bytes, shorts and ints) */
void BYTE_SCATTER(GenRegister src, uint32_t bti, uint32_t elemSize);
+ /*! DWord gather (for constant cache read) */
+ void DWORD_GATHER(GenRegister dst, GenRegister src, uint32_t bti);
/*! for scratch memory read */
void SCRATCH_READ(GenRegister msg, GenRegister dst, uint32_t offset, uint32_t size, uint32_t dst_num, uint32_t channel_mode);
/*! for scratch memory write */
diff --git a/backend/src/backend/gen_insn_gen7_schedule_info.hxx b/backend/src/backend/gen_insn_gen7_schedule_info.hxx
index 2204837..af2b0ee 100644
--- a/backend/src/backend/gen_insn_gen7_schedule_info.hxx
+++ b/backend/src/backend/gen_insn_gen7_schedule_info.hxx
@@ -22,6 +22,7 @@ DECL_GEN7_SCHEDULE(UntypedRead, 80, 1, 1)
DECL_GEN7_SCHEDULE(UntypedWrite, 80, 1, 1)
DECL_GEN7_SCHEDULE(ByteGather, 80, 1, 1)
DECL_GEN7_SCHEDULE(ByteScatter, 80, 1, 1)
+DECL_GEN7_SCHEDULE(DWordGather, 80, 1, 1)
DECL_GEN7_SCHEDULE(Sample, 80, 1, 1)
DECL_GEN7_SCHEDULE(TypedWrite, 80, 1, 1)
DECL_GEN7_SCHEDULE(SpillReg, 80, 1, 1)
diff --git a/backend/src/backend/gen_insn_selection.cpp b/backend/src/backend/gen_insn_selection.cpp
index bca08ba..1e81dac 100644
--- a/backend/src/backend/gen_insn_selection.cpp
+++ b/backend/src/backend/gen_insn_selection.cpp
@@ -506,6 +506,8 @@ namespace gbe
void BYTE_GATHER(Reg dst, Reg addr, uint32_t elemSize, uint32_t bti);
/*! Byte scatter (for unaligned bytes, shorts and ints) */
void BYTE_SCATTER(Reg addr, Reg src, uint32_t elemSize, uint32_t bti);
+ /*! DWord scatter (for constant cache read) */
+ void DWORD_GATHER(Reg dst, Reg addr, uint32_t bti);
/*! Extended math function (2 arguments) */
void MATH(Reg dst, uint32_t function, Reg src0, Reg src1);
/*! Extended math function (1 argument) */
@@ -993,6 +995,14 @@ namespace gbe
vector->reg = &insn->src(0);
}
+ void Selection::Opaque::DWORD_GATHER(Reg dst, Reg addr, uint32_t bti) {
+ SelectionInstruction *insn = this->appendInsn(SEL_OP_DWORD_GATHER, 1, 1);
+
+ insn->src(0) = addr;
+ insn->dst(0) = dst;
+ insn->extra.function = bti;
+ }
+
void Selection::Opaque::MATH(Reg dst, uint32_t function, Reg src0, Reg src1) {
SelectionInstruction *insn = this->appendInsn(SEL_OP_MATH, 1, 2);
insn->dst(0) = dst;
diff --git a/backend/src/backend/gen_insn_selection.hxx b/backend/src/backend/gen_insn_selection.hxx
index 32c7a05..89e1ef8 100644
--- a/backend/src/backend/gen_insn_selection.hxx
+++ b/backend/src/backend/gen_insn_selection.hxx
@@ -51,6 +51,7 @@ DECL_SELECTION_IR(READ64, Read64Instruction)
DECL_SELECTION_IR(WRITE64, Write64Instruction)
DECL_SELECTION_IR(BYTE_GATHER, ByteGatherInstruction)
DECL_SELECTION_IR(BYTE_SCATTER, ByteScatterInstruction)
+DECL_SELECTION_IR(DWORD_GATHER, DWordGatherInstruction)
DECL_SELECTION_IR(SAMPLE, SampleInstruction)
DECL_SELECTION_IR(TYPED_WRITE, TypedWriteInstruction)
DECL_SELECTION_IR(GET_IMAGE_INFO, GetImageInfoInstruction)
--
1.7.9.5
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