[Beignet] [PATCH] GBE: Use NOT instruction for unordered FCMP

[Zhigang Gong]

This patch causes a utest regression:
compiler_julia:
  compiler_julia()    [FAILED]
    Error: image mismatch
  at file /home/gongzg/git/fdo/beignet/utests/compiler_shader_toy.cpp, function run_kernel, line 65

Could you look into it? Thanks.

On Thu, Mar 27, 2014 at 11:31:23AM +0800, Ruiling Song wrote:
> this could save one possible loadi instruction.
> 
> Signed-off-by: Ruiling Song <ruiling.song at intel.com>
> ---
>  backend/src/backend/gen_insn_selection.cpp |    1 +
>  backend/src/ir/instruction.cpp             |    2 ++
>  backend/src/ir/instruction.hpp             |    2 ++
>  backend/src/ir/instruction.hxx             |    1 +
>  backend/src/llvm/llvm_gen_backend.cpp      |   28 ++++++++++++++--------------
>  5 files changed, 20 insertions(+), 14 deletions(-)
> 
> diff --git a/backend/src/backend/gen_insn_selection.cpp b/backend/src/backend/gen_insn_selection.cpp
> index 663ca64..0c60221 100644
> --- a/backend/src/backend/gen_insn_selection.cpp
> +++ b/backend/src/backend/gen_insn_selection.cpp
> @@ -1650,6 +1650,7 @@ namespace gbe
>            } else
>              sel.MOV(dst, src);
>            break;
> +        case ir::OP_NOT: sel.NOT(dst, src); break;
>          case ir::OP_RNDD: sel.RNDD(dst, src); break;
>          case ir::OP_RNDE: sel.RNDE(dst, src); break;
>          case ir::OP_RNDU: sel.RNDU(dst, src); break;
> diff --git a/backend/src/ir/instruction.cpp b/backend/src/ir/instruction.cpp
> index 2d2b34b..1ac9163 100644
> --- a/backend/src/ir/instruction.cpp
> +++ b/backend/src/ir/instruction.cpp
> @@ -775,6 +775,7 @@ namespace ir {
>          case OP_OR:
>          case OP_XOR:
>          case OP_AND:
> +        case OP_NOT:
>            CHECK_TYPE(this->type, logicalType);
>            break;
>          default:
> @@ -1489,6 +1490,7 @@ DECL_MEM_FN(GetImageInfoInstruction, const uint8_t, getImageIndex(void), getImag
>    DECL_EMIT_FUNCTION(FBL)
>    DECL_EMIT_FUNCTION(COS)
>    DECL_EMIT_FUNCTION(SIN)
> +  DECL_EMIT_FUNCTION(NOT)
>    DECL_EMIT_FUNCTION(LOG)
>    DECL_EMIT_FUNCTION(SQR)
>    DECL_EMIT_FUNCTION(RSQ)
> diff --git a/backend/src/ir/instruction.hpp b/backend/src/ir/instruction.hpp
> index 457b5b4..c0a81ee 100644
> --- a/backend/src/ir/instruction.hpp
> +++ b/backend/src/ir/instruction.hpp
> @@ -533,6 +533,8 @@ namespace ir {
>    Instruction ALU1(Opcode opcode, Type type, Register dst, Register src);
>    /*! mov.type dst src */
>    Instruction MOV(Type type, Register dst, Register src);
> +  /*! not.type dst src */
> +  Instruction NOT(Type type, Register dst, Register src);
>    /*! cos.type dst src */
>    Instruction COS(Type type, Register dst, Register src);
>    /*! sin.type dst src */
> diff --git a/backend/src/ir/instruction.hxx b/backend/src/ir/instruction.hxx
> index bebceff..27ea48d 100644
> --- a/backend/src/ir/instruction.hxx
> +++ b/backend/src/ir/instruction.hxx
> @@ -26,6 +26,7 @@
>   * \author Benjamin Segovia <benjamin.segovia at intel.com>
>   */
>  DECL_INSN(MOV, UnaryInstruction)
> +DECL_INSN(NOT, UnaryInstruction)
>  DECL_INSN(COS, UnaryInstruction)
>  DECL_INSN(SIN, UnaryInstruction)
>  DECL_INSN(LOG, UnaryInstruction)
> diff --git a/backend/src/llvm/llvm_gen_backend.cpp b/backend/src/llvm/llvm_gen_backend.cpp
> index 467e240..573104e 100644
> --- a/backend/src/llvm/llvm_gen_backend.cpp
> +++ b/backend/src/llvm/llvm_gen_backend.cpp
> @@ -1747,33 +1747,33 @@ namespace gbe
>          else if(isa<ConstantFP>(I.getOperand(1)))
>            ctx.NE(type, dst, src0, src0);
>          else {
> -          ctx.ORD(type, tmp, src0, src1);
> -          ctx.XOR(insnType, dst, tmp, getRegister(cv));  //TODO: Use NOT directly
> +          ctx.ORD(type, dst, src0, src1);
> +          ctx.NOT(insnType, dst, dst);
>          }
>          break;
>        case ICmpInst::FCMP_UEQ:
> -        ctx.NE(type, tmp, src0, src1);
> -        ctx.XOR(insnType, dst, tmp, getRegister(cv));
> +        ctx.NE(type, dst, src0, src1);
> +        ctx.NOT(insnType, dst, dst);
>          break;
>        case ICmpInst::FCMP_UGT:
> -        ctx.LE(type, tmp, src0, src1);
> -        ctx.XOR(insnType, dst, tmp, getRegister(cv));
> +        ctx.LE(type, dst, src0, src1);
> +        ctx.NOT(insnType, dst, dst);
>          break;
>        case ICmpInst::FCMP_UGE:
> -        ctx.LT(type, tmp, src0, src1);
> -        ctx.XOR(insnType, dst, tmp, getRegister(cv));
> +        ctx.LT(type, dst, src0, src1);
> +        ctx.NOT(insnType, dst, dst);
>          break;
>        case ICmpInst::FCMP_ULT:
> -        ctx.GE(type, tmp, src0, src1);
> -        ctx.XOR(insnType, dst, tmp, getRegister(cv));
> +        ctx.GE(type, dst, src0, src1);
> +        ctx.NOT(insnType, dst, dst);
>          break;
>        case ICmpInst::FCMP_ULE:
> -        ctx.GT(type, tmp, src0, src1);
> -        ctx.XOR(insnType, dst, tmp, getRegister(cv));
> +        ctx.GT(type, dst, src0, src1);
> +        ctx.NOT(insnType, dst, dst);
>          break;
>        case ICmpInst::FCMP_UNE:
> -        ctx.EQ(type, tmp, src0, src1);
> -        ctx.XOR(insnType, dst, tmp, getRegister(cv));
> +        ctx.EQ(type, dst, src0, src1);
> +        ctx.NOT(insnType, dst, dst);
>          break;
>        case ICmpInst::FCMP_TRUE:
>          ctx.MOV(insnType, dst, getRegister(cv));
> -- 
> 1.7.9.5
> 
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