[Beignet] [PATCH 16/18] GBE: Add two helper scalar registers to hold 0 and all 1s.

[Gong, Zhigang]

> -----Original Message-----
> From: Yang, Rong R
> Sent: Wednesday, April 2, 2014 4:46 PM
> To: Gong, Zhigang; beignet at lists.freedesktop.org
> Cc: Gong, Zhigang
> Subject: RE: [Beignet] [PATCH 16/18] GBE: Add two helper scalar registers to
> hold 0 and all 1s.
> 
> One comment.
> 
> -----Original Message-----
> From: Beignet [mailto:beignet-bounces at lists.freedesktop.org] On Behalf Of
> Zhigang Gong
> Sent: Friday, March 28, 2014 3:11 PM
> To: beignet at lists.freedesktop.org
> Cc: Gong, Zhigang
> Subject: [Beignet] [PATCH 16/18] GBE: Add two helper scalar registers to hold 0
> and all 1s.
> 
> Signed-off-by: Zhigang Gong <zhigang.gong at intel.com>
> ---
>  backend/src/backend/gen_context.cpp | 9 +++++++++
>  backend/src/backend/program.h       | 2 ++
>  backend/src/ir/profile.cpp          | 6 ++++--
>  backend/src/ir/profile.hpp          | 6 ++++--
>  4 files changed, 19 insertions(+), 4 deletions(-)
> 
> diff --git a/backend/src/backend/gen_context.cpp
> b/backend/src/backend/gen_context.cpp
> index 6cfeca4..ec778d2 100644
> --- a/backend/src/backend/gen_context.cpp
> +++ b/backend/src/backend/gen_context.cpp
> @@ -105,12 +105,19 @@ namespace gbe
>      // when group size not aligned to simdWidth, flag register need clear to
>      // make prediction(any8/16h) work correctly
>      const GenRegister blockip =
> ra->genReg(GenRegister::uw8grf(ir::ocl::blockip));
> +    const GenRegister zero =
> ra->genReg(GenRegister::uw1grf(ir::ocl::zero));
> +    const GenRegister one =
> + ra->genReg(GenRegister::uw1grf(ir::ocl::one));
>      p->push();
>        p->curr.noMask = 1;
>        p->curr.predicate = GEN_PREDICATE_NONE;
>        p->MOV(blockip, GenRegister::immuw(GEN_MAX_LABEL));
>        p->curr.noMask = 0;
>        p->MOV(blockip, GenRegister::immuw(0));
> +      p->curr.execWidth = 1;
> +      // FIXME, need to get the final use set of zero/one, if there is no user,
> +      // no need to generate the following two instructions.
> +      p->MOV(zero, GenRegister::immuw(0));
> +      p->MOV(one, GenRegister::immw(-1));
> 
> >>>>>>> Is zero and one only for compare instruction in gen_sel_insn? ocl::one
> is not common 1, actually, it's -1.

Currently，it only used by the CMP instruction when the destination register need
to be write back according to the current flag result.

But it can be used by any other instruction in the future. Maybe one is not a very good name.
We may change it in the future.

> 
>      p->pop();
>    }
> 
> @@ -1902,6 +1909,8 @@ namespace gbe
>      allocCurbeReg(lid0, GBE_CURBE_LOCAL_ID_X);
>      allocCurbeReg(lid1, GBE_CURBE_LOCAL_ID_Y);
>      allocCurbeReg(lid2, GBE_CURBE_LOCAL_ID_Z);
> +    allocCurbeReg(zero, GBE_CURBE_ZERO);
> +    allocCurbeReg(one, GBE_CURBE_ONE);
>      if (stackUse.size() != 0)
>        allocCurbeReg(stackbuffer, GBE_CURBE_EXTRA_ARGUMENT,
> GBE_STACK_BUFFER);
>      // Go over the arguments and find the related patch locations diff --git
> a/backend/src/backend/program.h b/backend/src/backend/program.h index
> 4ca7277..c22793e 100644
> --- a/backend/src/backend/program.h
> +++ b/backend/src/backend/program.h
> @@ -76,6 +76,8 @@ enum gbe_curbe_type {
>    GBE_CURBE_EXTRA_ARGUMENT,
>    GBE_CURBE_BLOCK_IP,
>    GBE_CURBE_THREAD_NUM,
> +  GBE_CURBE_ZERO,
> +  GBE_CURBE_ONE,
>  };
> 
>  /*! Extra arguments use the negative range of sub-values */ diff --git
> a/backend/src/ir/profile.cpp b/backend/src/ir/profile.cpp index
> 2a1bb41..ddf53d1 100644
> --- a/backend/src/ir/profile.cpp
> +++ b/backend/src/ir/profile.cpp
> @@ -39,8 +39,8 @@ namespace ir {
>          "global_offset_0", "global_offset_1", "global_offset_2",
>          "stack_pointer", "stack_buffer",
>          "block_ip",
> -        "barrier_id", "thread_number",
> -        "work_dimension",
> +        "barrier_id", "thread_number", "work_dimension",
> +        "zero", "one",
>          "retVal"
>      };
> 
> @@ -78,6 +78,8 @@ namespace ir {
>        DECL_NEW_REG(FAMILY_DWORD, barrierid, 1);
>        DECL_NEW_REG(FAMILY_DWORD, threadn, 1);
>        DECL_NEW_REG(FAMILY_DWORD, workdim, 1);
> +      DECL_NEW_REG(FAMILY_DWORD, zero, 1);
> +      DECL_NEW_REG(FAMILY_DWORD, one, 1);
>        DECL_NEW_REG(FAMILY_WORD, retVal, 1);
>      }
>  #undef DECL_NEW_REG
> diff --git a/backend/src/ir/profile.hpp b/backend/src/ir/profile.hpp index
> c4763c8..0652a25 100644
> --- a/backend/src/ir/profile.hpp
> +++ b/backend/src/ir/profile.hpp
> @@ -65,8 +65,10 @@ namespace ir {
>      static const Register barrierid = Register(21);// barrierid
>      static const Register threadn = Register(22);  // number of threads
>      static const Register workdim = Register(23);  // work dimention.
> -    static const Register retVal = Register(24);   // helper register to do
> data flow analysis.
> -    static const uint32_t regNum = 25;             // number of special
> registers
> +    static const Register zero = Register(24);     //  scalar register holds
> zero.
> +    static const Register one = Register(25);     //  scalar register holds
> one.
> +    static const Register retVal = Register(26);   // helper register to do
> data flow analysis.
> +    static const uint32_t regNum = 27;             // number of special
> registers
>      extern const char *specialRegMean[];           // special register
> name.
>    } /* namespace ocl */
> 
> --
> 1.8.3.2
> 
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