[Beignet] [PATCH 1/3] enable mad for mul+sub.

[Ruiling Song]

Signed-off-by: Ruiling Song <ruiling.song at intel.com>
---
 backend/src/backend/gen_insn_selection.cpp |    7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/backend/src/backend/gen_insn_selection.cpp b/backend/src/backend/gen_insn_selection.cpp
index d0e3d0b..463d36e 100644
--- a/backend/src/backend/gen_insn_selection.cpp
+++ b/backend/src/backend/gen_insn_selection.cpp
@@ -2066,6 +2066,7 @@ namespace gbe
     /*! Register the pattern for all opcodes of the family */
     MulAddInstructionPattern(void) : SelectionPattern(2, 1) {
        this->opcodes.push_back(ir::OP_ADD);
+       this->opcodes.push_back(ir::OP_SUB);
     }
 
     /*! Implements base class */
@@ -2095,7 +2096,8 @@ namespace gbe
         GBE_ASSERT(cast<ir::BinaryInstruction>(child0->insn).getType() == TYPE_FLOAT);
         const GenRegister src0 = sel.selReg(child0->insn.getSrc(0), TYPE_FLOAT);
         const GenRegister src1 = sel.selReg(child0->insn.getSrc(1), TYPE_FLOAT);
-        const GenRegister src2 = sel.selReg(insn.getSrc(1), TYPE_FLOAT);
+        GenRegister src2 = sel.selReg(insn.getSrc(1), TYPE_FLOAT);
+        if(insn.getOpcode() == ir::OP_SUB) src2 = GenRegister::negate(src2);
         sel.MAD(dst, src2, src0, src1); // order different on HW!
         if (child0->child[0]) child0->child[0]->isRoot = 1;
         if (child0->child[1]) child0->child[1]->isRoot = 1;
@@ -2104,9 +2106,10 @@ namespace gbe
       }
       if (child1 && child1->insn.getOpcode() == OP_MUL) {
         GBE_ASSERT(cast<ir::BinaryInstruction>(child1->insn).getType() == TYPE_FLOAT);
-        const GenRegister src0 = sel.selReg(child1->insn.getSrc(0), TYPE_FLOAT);
+        GenRegister src0 = sel.selReg(child1->insn.getSrc(0), TYPE_FLOAT);
         const GenRegister src1 = sel.selReg(child1->insn.getSrc(1), TYPE_FLOAT);
         const GenRegister src2 = sel.selReg(insn.getSrc(0), TYPE_FLOAT);
+        if(insn.getOpcode() == ir::OP_SUB) src0 = GenRegister::negate(src0);
         sel.MAD(dst, src2, src0, src1); // order different on HW!
         if (child1->child[0]) child1->child[0]->isRoot = 1;
         if (child1->child[1]) child1->child[1]->isRoot = 1;
-- 
1.7.10.4