[Beignet] [PATCH] Separate flush and invalidate in function intel_gpgpu_pipe_control.

[Zhenyu Wang]

On 2014.12.26 14:57:58 +0800, Yang Rong wrote:
> From: Luo Xionghu <xionghu.luo at intel.com>
> 
> HSW has a limitation when PIPECONTROL with RO Cache Invalidation:
> Prior to programming a PIPECONTROL command with any of the RO cache invalidation bit set,
> program a PIPECONTROL flush command with CS stall bit and HDC Flush bit set.
> 
> So must use two PIPECONTROL commands to flush and invalidate L3 cache in HSW.
> This patch fix some random fails which has very heavy DC read/write in HSW.
> ---

yeah, I've also noticed the bit for DC flush when did experiment on
BDW, and I haven't got a good case to produce any issue if we didn't
set that.
                                                                                                                                                                                               
And this fix should go to kernel ring flush code where we take care of
all flush and invalidate with proper workarounds. Actual I've made a
patch for that, but look for good case to trigger the issue, what's
your actual case?

-- 
Open Source Technology Center, Intel ltd.

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