[Beignet] [PATCH 1/2] GBE: Reduce random behaviour of the code generation

[Zhigang Gong]

There are two major types of random behviour source. One is the
register spill tick. Now we fix it to increase from 0 for
each new code generation.
The second random source is the register sorting. When two
register has the same startID or endID,  their sorting order
is not determined and maybe random in different machine. This
patch mitigate this random source by introduce another comparison
if the main key is identical.

Signed-off-by: Zhigang Gong <zhigang.gong at intel.com>
---
 backend/src/backend/gen_context.cpp        |  2 ++
 backend/src/backend/gen_context.hpp        |  1 +
 backend/src/backend/gen_reg_allocation.cpp | 15 +++++++++++----
 3 files changed, 14 insertions(+), 4 deletions(-)

diff --git a/backend/src/backend/gen_context.cpp b/backend/src/backend/gen_context.cpp
index 1db6e1f..ba4a8f8 100644
--- a/backend/src/backend/gen_context.cpp
+++ b/backend/src/backend/gen_context.cpp
@@ -50,6 +50,7 @@ namespace gbe
     this->sel = NULL;
     this->ra = NULL;
     this->ifEndifFix = false;
+    this->regSpillTick = 0;
   }
 
   GenContext::~GenContext(void) {
@@ -72,6 +73,7 @@ namespace gbe
     this->branchPos3.clear();
     this->labelPos.clear();
     this->errCode = NO_ERROR;
+    this->regSpillTick = 0;
   }
 
   void GenContext::newSelection(void) {
diff --git a/backend/src/backend/gen_context.hpp b/backend/src/backend/gen_context.hpp
index 02c83d0..088798d 100644
--- a/backend/src/backend/gen_context.hpp
+++ b/backend/src/backend/gen_context.hpp
@@ -206,6 +206,7 @@ namespace gbe
   private:
     CompileErrorCode errCode;
     bool ifEndifFix;
+    uint32_t regSpillTick;
     /*! Build the curbe patch list for the given kernel */
     void buildPatchList(void);
     /*! Calc the group's slm offset from R0.0, to work around HSW SLM bug*/
diff --git a/backend/src/backend/gen_reg_allocation.cpp b/backend/src/backend/gen_reg_allocation.cpp
index b7fbc93..524eb76 100644
--- a/backend/src/backend/gen_reg_allocation.cpp
+++ b/backend/src/backend/gen_reg_allocation.cpp
@@ -353,7 +353,15 @@ namespace gbe
 
   template <bool sortStartingPoint>
   inline bool cmp(const GenRegInterval *i0, const GenRegInterval *i1) {
-    return sortStartingPoint ? i0->minID < i1->minID : i0->maxID < i1->maxID;
+    if (sortStartingPoint) {
+      if (i0->minID == i1->minID)
+        return (i0->maxID < i1->maxID);
+      return i0->minID < i1->minID;
+    } else {
+      if (i0->maxID == i1->maxID)
+        return (i0->minID < i1->minID);
+      return i0->maxID < i1->maxID;
+    }
   }
 
   bool GenRegAllocator::Opaque::expireGRF(const GenRegInterval &limit) {
@@ -943,15 +951,14 @@ namespace gbe
                                                        uint32_t size,
                                                        uint32_t alignment) {
     uint32_t grfOffset;
-    static uint32_t tick = 0;
     // Doing expireGRF too freqently will cause the post register allocation
     // scheduling very hard. As it will cause a very high register conflict rate.
     // The tradeoff here is to reduce the freqency here. And if we are under spilling
     // then no need to reduce that freqency as the register pressure is the most
     // important factor.
-    if (tick % 12 == 0 || ctx.reservedSpillRegs != 0)
+    if (ctx.regSpillTick % 12 == 0 || ctx.reservedSpillRegs != 0)
       this->expireGRF(interval);
-    tick++;
+    ctx.regSpillTick++;
     // For some scalar byte register, it may be used as a destination register
     // and the source is a scalar Dword. If that is the case, the byte register
     // must get 4byte alignment register offset.
-- 
1.8.3.2