[Beignet] [PATCH] GBE: fix one illegal instruction.

[Yang, Rong R]

LGTM, thanks.

-----Original Message-----
From: Beignet [mailto:beignet-bounces at lists.freedesktop.org] On Behalf Of Zhigang Gong
Sent: Monday, June 09, 2014 9:46 AM
To: beignet at lists.freedesktop.org
Cc: Gong, Zhigang
Subject: [Beignet] [PATCH] GBE: fix one illegal instruction.

When the destination is a scalar and the execution width is 1, we should use scalar vec rather.

This patch fix the following illegal instruction:
  (38      )  mov(1)          g124.3<1>:F     acc0<8,8,1>:F
to the correct one:
  (38      )  mov(1)          g124.3<1>:F     acc0<0,1,0>:F

Signed-off-by: Zhigang Gong <zhigang.gong at intel.com>
---
 backend/src/backend/gen_insn_selection.cpp | 9 +++++++--
 backend/src/backend/gen_register.hpp       | 7 +++++++
 2 files changed, 14 insertions(+), 2 deletions(-)

diff --git a/backend/src/backend/gen_insn_selection.cpp b/backend/src/backend/gen_insn_selection.cpp
index 74f2cf5..c4c77e7 100644
--- a/backend/src/backend/gen_insn_selection.cpp
+++ b/backend/src/backend/gen_insn_selection.cpp
@@ -2439,8 +2439,13 @@ namespace gbe
         sel.curr.accWrEnable = 1;
         sel.MACH(GenRegister::retype(GenRegister::null(), GEN_TYPE_D), src0, src1);
         sel.curr.accWrEnable = 0;
-        sel.curr.execWidth = simdWidth != 1 ? 8 : 1;;
-        sel.MOV(GenRegister::retype(dst, GEN_TYPE_F), GenRegister::acc());
+        if (simdWidth == 1) {
+          sel.curr.execWidth = 1;
+          sel.MOV(GenRegister::retype(dst, GEN_TYPE_F), GenRegister::vec1(GenRegister::acc()));
+        } else {
+          sel.curr.execWidth = 8;
+          sel.MOV(GenRegister::retype(dst, GEN_TYPE_F), GenRegister::acc());
+        }
 
         // Right part of the 16-wide register now
         if (simdWidth == 16) {
diff --git a/backend/src/backend/gen_register.hpp b/backend/src/backend/gen_register.hpp
index 3967e6e..da58c06 100644
--- a/backend/src/backend/gen_register.hpp
+++ b/backend/src/backend/gen_register.hpp
@@ -687,6 +687,13 @@ namespace gbe
               && reg.nr == GEN_ARF_NULL);
     }
 
+    static INLINE GenRegister vec1(GenRegister reg) {
+      reg.width = GEN_WIDTH_1;
+      reg.hstride = GEN_HORIZONTAL_STRIDE_0;
+      reg.vstride = GEN_VERTICAL_STRIDE_0;
+      return reg;
+    }
+
     static INLINE GenRegister acc(void) {
       return GenRegister(GEN_ARCHITECTURE_REGISTER_FILE,
                          GEN_ARF_ACCUMULATOR,
--
1.8.3.2

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