[Beignet] [PATCH 2/3] Enable the 1D and 2D image support in run time.
junyan.he at inbox.com
junyan.he at inbox.com
Mon Jun 16 21:06:54 PDT 2014
From: Junyan He <junyan.he at linux.intel.com>
Signed-off-by: Junyan He <junyan.he at linux.intel.com>
---
src/cl_mem.c | 30 ++++++++++++++++++----------
src/intel/intel_gpgpu.c | 52 +++++++++++++++++++++++++++++++++++++++----------
2 files changed, 62 insertions(+), 20 deletions(-)
diff --git a/src/cl_mem.c b/src/cl_mem.c
index b4a5d81..0806d35 100644
--- a/src/cl_mem.c
+++ b/src/cl_mem.c
@@ -44,10 +44,6 @@
return CL_INVALID_VALUE; \
break;
-#define CL_MEM_OBJECT_BUFFER 0x10F0
-#define CL_MEM_OBJECT_IMAGE2D 0x10F1
-#define CL_MEM_OBJECT_IMAGE3D 0x10F2
-
#define MAX_TILING_SIZE 128 * MB
static cl_mem_object_type
@@ -596,7 +592,8 @@ _cl_mem_new_image(cl_context ctx,
if (UNLIKELY(data && min_pitch > pitch)) DO_IMAGE_ERROR;
if (UNLIKELY(!data && pitch != 0)) DO_IMAGE_ERROR;
tiling = CL_NO_TILE;
- } else if (image_type == CL_MEM_OBJECT_IMAGE2D) {
+ } else if (image_type == CL_MEM_OBJECT_IMAGE2D ||
+ image_type == CL_MEM_OBJECT_IMAGE1D_ARRAY) {
size_t min_pitch = bpp * w;
if (data && pitch == 0)
pitch = min_pitch;
@@ -608,8 +605,13 @@ _cl_mem_new_image(cl_context ctx,
/* Pick up tiling mode (we do only linear on SNB) */
if (cl_driver_get_ver(ctx->drv) != 6)
tiling = cl_get_default_tiling();
+
+ if (image_type == CL_MEM_OBJECT_IMAGE1D_ARRAY)
+ tiling = CL_NO_TILE;
+
depth = 1;
- } else if (image_type == CL_MEM_OBJECT_IMAGE3D) {
+ } else if (image_type == CL_MEM_OBJECT_IMAGE3D ||
+ image_type == CL_MEM_OBJECT_IMAGE2D_ARRAY) {
size_t min_pitch = bpp * w;
if (data && pitch == 0)
pitch = min_pitch;
@@ -660,8 +662,9 @@ _cl_mem_new_image(cl_context ctx,
goto error;
cl_buffer_set_tiling(mem->bo, tiling, aligned_pitch);
- aligned_slice_pitch = (image_type == CL_MEM_OBJECT_IMAGE1D
- || image_type == CL_MEM_OBJECT_IMAGE2D) ? 0 : aligned_pitch * ALIGN(h, 2);
+ aligned_slice_pitch = (image_type == CL_MEM_OBJECT_IMAGE1D || image_type == CL_MEM_OBJECT_IMAGE2D
+ || image_type == CL_MEM_OBJECT_IMAGE1D_ARRAY || image_type == CL_MEM_OBJECT_IMAGE1D_BUFFER)
+ ? 0 : aligned_pitch * ALIGN(h, 2);
cl_mem_image_init(cl_mem_image(mem), w, h, image_type, depth, *fmt,
intel_fmt, bpp, aligned_pitch, aligned_slice_pitch, tiling,
@@ -828,9 +831,16 @@ cl_mem_new_image(cl_context context,
image_desc->image_width, image_desc->image_height, image_desc->image_depth,
image_desc->image_row_pitch, image_desc->image_slice_pitch,
host_ptr, errcode_ret);
- case CL_MEM_OBJECT_IMAGE2D_ARRAY:
case CL_MEM_OBJECT_IMAGE1D_ARRAY:
- NOT_IMPLEMENTED;
+ return _cl_mem_new_image(context, flags, image_format, image_desc->image_type,
+ image_desc->image_width, image_desc->image_array_size, image_desc->image_depth,
+ image_desc->image_row_pitch, image_desc->image_slice_pitch,
+ host_ptr, errcode_ret);
+ case CL_MEM_OBJECT_IMAGE2D_ARRAY:
+ return _cl_mem_new_image(context, flags, image_format, image_desc->image_type,
+ image_desc->image_width, image_desc->image_height, image_desc->image_array_size,
+ image_desc->image_row_pitch, image_desc->image_slice_pitch,
+ host_ptr, errcode_ret);
case CL_MEM_OBJECT_IMAGE1D_BUFFER:
return _cl_mem_new_image_from_buffer(context, flags, image_format,
image_desc, errcode_ret);
diff --git a/src/intel/intel_gpgpu.c b/src/intel/intel_gpgpu.c
index 1da6400..fedfcce 100644
--- a/src/intel/intel_gpgpu.c
+++ b/src/intel/intel_gpgpu.c
@@ -712,18 +712,31 @@ intel_gpgpu_map_address_space(intel_gpgpu_t *gpgpu)
}
static int
+intel_is_surface_array(cl_mem_object_type type)
+{
+ if (type == CL_MEM_OBJECT_IMAGE1D_ARRAY ||
+ type == CL_MEM_OBJECT_IMAGE2D_ARRAY)
+ return 1;
+
+ return 0;
+}
+
+static int
intel_get_surface_type(cl_mem_object_type type)
{
switch (type) {
case CL_MEM_OBJECT_IMAGE1D_BUFFER:
- case CL_MEM_OBJECT_IMAGE1D: return I965_SURFACE_1D;
+ case CL_MEM_OBJECT_IMAGE1D:
+ case CL_MEM_OBJECT_IMAGE1D_ARRAY:
+ return I965_SURFACE_1D;
- case CL_MEM_OBJECT_IMAGE2D: return I965_SURFACE_2D;
- case CL_MEM_OBJECT_IMAGE3D: return I965_SURFACE_3D;
+ case CL_MEM_OBJECT_IMAGE2D:
case CL_MEM_OBJECT_IMAGE2D_ARRAY:
- case CL_MEM_OBJECT_IMAGE1D_ARRAY:
- NOT_IMPLEMENTED;
- break;
+ return I965_SURFACE_2D;
+
+ case CL_MEM_OBJECT_IMAGE3D:
+ return I965_SURFACE_3D;
+
default:
assert(0);
}
@@ -749,11 +762,21 @@ intel_gpgpu_bind_image_gen7(intel_gpgpu_t *gpgpu,
memset(ss, 0, sizeof(*ss));
ss->ss0.surface_type = intel_get_surface_type(type);
+ if (intel_is_surface_array(type)) {
+ ss->ss0.surface_array = 1;
+ ss->ss0.surface_array_spacing = 1;
+ }
ss->ss0.surface_format = format;
ss->ss1.base_addr = obj_bo->offset;
ss->ss2.width = w - 1;
- ss->ss2.height = h - 1;
- ss->ss3.depth = depth - 1;
+
+ if (type == CL_MEM_OBJECT_IMAGE1D_ARRAY) {
+ ss->ss2.height = 1;
+ ss->ss3.depth = h - 1;
+ } else {
+ ss->ss2.height = h - 1;
+ ss->ss3.depth = depth - 1;
+ }
ss->ss4.not_str_buf.rt_view_extent = depth - 1;
ss->ss4.not_str_buf.min_array_element = 0;
ss->ss3.pitch = pitch - 1;
@@ -790,11 +813,20 @@ intel_gpgpu_bind_image_gen75(intel_gpgpu_t *gpgpu,
memset(ss, 0, sizeof(*ss));
ss->ss0.surface_type = intel_get_surface_type(type);
+ if (intel_is_surface_array(type)) {
+ ss->ss0.surface_array = 1;
+ ss->ss0.surface_array_spacing = 1;
+ }
ss->ss0.surface_format = format;
ss->ss1.base_addr = obj_bo->offset;
ss->ss2.width = w - 1;
- ss->ss2.height = h - 1;
- ss->ss3.depth = depth - 1;
+ if (type == CL_MEM_OBJECT_IMAGE1D_ARRAY) {
+ ss->ss2.height = 1;
+ ss->ss3.depth = h - 1;
+ } else {
+ ss->ss2.height = h - 1;
+ ss->ss3.depth = depth - 1;
+ }
ss->ss4.not_str_buf.rt_view_extent = depth - 1;
ss->ss4.not_str_buf.min_array_element = 0;
ss->ss3.pitch = pitch - 1;
--
1.8.3.2
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