[Beignet] [PATCH 14/18] GBE: one instruction is enough for SEL_CMP now.

[Zhigang Gong]

As we have if/endif, now the SEL_CMP could write to the
dst register directly with correct emask.

Signed-off-by: Zhigang Gong <zhigang.gong at intel.com>
---
 backend/src/backend/gen_insn_selection.cpp | 7 +------
 1 file changed, 1 insertion(+), 6 deletions(-)

diff --git a/backend/src/backend/gen_insn_selection.cpp b/backend/src/backend/gen_insn_selection.cpp
index afe6392..560d3dc 100644
--- a/backend/src/backend/gen_insn_selection.cpp
+++ b/backend/src/backend/gen_insn_selection.cpp
@@ -2107,22 +2107,17 @@ namespace gbe
       // Like for regular selects, we need a temporary since we cannot predicate
       // properly
       const ir::Type type = cmpInsn.getType();
-      const RegisterFamily family = getFamily(type);
-      const GenRegister tmp = sel.selReg(sel.reg(family), type);
       const uint32_t simdWidth = sel.curr.execWidth;
       const GenRegister dst  = sel.selReg(insn.getDst(0), type);
       const GenRegister src0 = sel.selReg(cmpInsn.getSrc(0), type);
       const GenRegister src1 = sel.selReg(cmpInsn.getSrc(1), type);
 
       sel.push();
-        sel.curr.noMask = 1;
         sel.curr.predicate = GEN_PREDICATE_NONE;
         sel.curr.execWidth = simdWidth;
-        sel.SEL_CMP(genCmp, tmp, src0, src1);
+        sel.SEL_CMP(genCmp, dst, src0, src1);
       sel.pop();
 
-      // Update the destination register properly now
-      sel.MOV(dst, tmp);
 
       // We need the sources of the compare instruction
       markAllChildren(*cmp);
-- 
1.8.3.2