[Beignet] [PATCH 3/8] Enable pipe control.

[Yang Rong]

The previour pipe control don't work, because it don't advance the batch buffer.
So the value set in function intel_gpgpu_pipe_control will be flushed later. Fix it.

Signed-off-by: Yang Rong <rong.r.yang at intel.com>
---
 src/intel/intel_gpgpu.c   | 4 ++--
 src/intel/intel_structs.h | 8 ++++++--
 2 files changed, 8 insertions(+), 4 deletions(-)

diff --git a/src/intel/intel_gpgpu.c b/src/intel/intel_gpgpu.c
index 3d6fd30..603a075 100644
--- a/src/intel/intel_gpgpu.c
+++ b/src/intel/intel_gpgpu.c
@@ -313,9 +313,8 @@ intel_gpgpu_write_timestamp(intel_gpgpu_t *gpgpu, int idx)
 static void
 intel_gpgpu_pipe_control(intel_gpgpu_t *gpgpu)
 {
-  BEGIN_BATCH(gpgpu->batch, SIZEOF32(gen6_pipe_control_t));
   gen6_pipe_control_t* pc = (gen6_pipe_control_t*)
-    intel_batchbuffer_alloc_space(gpgpu->batch, 0);
+    intel_batchbuffer_alloc_space(gpgpu->batch, sizeof(gen6_pipe_control_t));
   memset(pc, 0, sizeof(*pc));
   pc->dw0.length = SIZEOF32(gen6_pipe_control_t) - 2;
   pc->dw0.instruction_subopcode = GEN7_PIPE_CONTROL_SUBOPCODE_3D_CONTROL;
@@ -326,6 +325,7 @@ intel_gpgpu_pipe_control(intel_gpgpu_t *gpgpu)
   pc->dw1.texture_cache_invalidation_enable = 1;
   pc->dw1.cs_stall = 1;
   pc->dw1.dc_flush_enable = 1;
+  //pc->dw1.instruction_cache_invalidate_enable = 1;
   ADVANCE_BATCH(gpgpu->batch);
 }
 
diff --git a/src/intel/intel_structs.h b/src/intel/intel_structs.h
index 59a9810..ef76bb4 100644
--- a/src/intel/intel_structs.h
+++ b/src/intel/intel_structs.h
@@ -351,8 +351,12 @@ typedef struct gen6_pipe_control
   } dw2;
 
   struct {
-    uint64_t data;
-  } qw0;
+    uint32_t data;
+  } dw3;
+
+  struct {
+    uint32_t data;
+  } dw4;
 } gen6_pipe_control_t;
 
 typedef struct gen6_sampler_state
-- 
1.8.3.2