[Beignet] [PATCH 0/5] Implement uniform value analysis and optimization.

Song, Ruiling ruiling.song at intel.com
Tue May 13 00:13:20 PDT 2014


The patchset looks good to me.

-----Original Message-----
From: Beignet [mailto:beignet-bounces at lists.freedesktop.org] On Behalf Of Zhigang Gong
Sent: Thursday, May 08, 2014 3:57 PM
To: beignet at lists.freedesktop.org
Cc: Gong, Zhigang
Subject: [Beignet] [PATCH 0/5] Implement uniform value analysis and optimization.

This patchset is mainly for uniform analysis and optimization. The first
2 patches are preparation. And then 3 patches to implement the analysis and optimization. This patchset could reduce the register pressure for many cases, especially those kernels which have more scalar codes.

For luxmark, it doesn't bring too much difference. But does reduce the register spilling on SIMD16 mode.
For opencv, it bring 10% performance gain for some cases.

The whole patch set is the preparation to the following two further
optimization:
1. consolidate multiple uniform load/store into one load/store.
2. mix simd16 into simd8 mode.

Zhigang Gong (5):
  GBE: don't need to compute liveout again in value.cpp.
  GBE: change scalar byte size to 2 from 1.
  GBE: implement uniform analysis.
  GBE: enable uniform for load instruction.
  GBE: enable uniform analysis for bool data type.

 backend/src/backend/gen_encoder.cpp        |   6 +-
 backend/src/backend/gen_insn_selection.cpp | 415 ++++++++++++++++++-----------  backend/src/backend/gen_reg_allocation.cpp |  53 +++-
 backend/src/ir/function.hpp                |   5 +
 backend/src/ir/liveness.cpp                |  10 +
 backend/src/ir/register.hpp                |   5 +
 backend/src/ir/value.cpp                   |  33 ---
 backend/src/llvm/llvm_gen_backend.cpp      |   1 +
 8 files changed, 326 insertions(+), 202 deletions(-)

--
1.8.3.2

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