[Beignet] [PATCH 2/3] GBE: Fix replaceSrc replaceDst for long data type.

[Ruiling Song]

As we change register layout for long/ulong.
we can not use double move to deal with long/ulong move

Signed-off-by: Ruiling Song <ruiling.song at intel.com>
---
 backend/src/backend/gen_insn_selection.cpp |   20 +++++++++++++-------
 1 file changed, 13 insertions(+), 7 deletions(-)

diff --git a/backend/src/backend/gen_insn_selection.cpp b/backend/src/backend/gen_insn_selection.cpp
index 3f7154f..000857f 100644
--- a/backend/src/backend/gen_insn_selection.cpp
+++ b/backend/src/backend/gen_insn_selection.cpp
@@ -859,17 +859,23 @@ namespace gbe
     const uint32_t simdWidth = insn->state.execWidth;
     ir::Register tmp;
 
+    const GenRegister src = insn->src(regID);
+    ir::RegisterFamily f = file.get(src.reg()).family;
+
     // This will append the temporary register in the instruction block
     this->block = block;
-    tmp = this->reg(ir::FAMILY_DWORD);
+    tmp = this->reg(f);
 
     // Generate the MOV instruction and replace the register in the instruction
     SelectionInstruction *mov = this->create(SEL_OP_MOV, 1, 1);
-    mov->src(0) = GenRegister::retype(insn->src(regID), GEN_TYPE_F);
+    mov->src(0) = src;
     mov->state = GenInstructionState(simdWidth);
+
     if (this->isScalarReg(insn->src(regID).reg()))
       mov->state.noMask = 1;
-    insn->src(regID) = mov->dst(0) = GenRegister::fxgrf(simdWidth, tmp);
+
+    GenRegister gr = (f == ir::FAMILY_QWORD) ? GenRegister::dfxgrf(simdWidth, tmp) : GenRegister::fxgrf(simdWidth, tmp);
+    insn->src(regID) = mov->dst(0) = GenRegister::retype(gr, src.type);
     insn->prepend(*mov);
 
     return tmp;
@@ -879,8 +885,8 @@ namespace gbe
     SelectionBlock *block = insn->parent;
     uint32_t simdWidth = this->isScalarReg(insn->dst(regID).reg()) ? 1 : insn->state.execWidth;
     ir::Register tmp;
-    ir::RegisterFamily f = file.get(insn->dst(regID).reg()).family;
-    int genType = f == ir::FAMILY_QWORD ? GEN_TYPE_DF : GEN_TYPE_F;
+    const GenRegister dst = insn->dst(regID);
+    ir::RegisterFamily f = file.get(dst.reg()).family;
     GenRegister gr;
 
     // This will append the temporary register in the instruction block
@@ -889,12 +895,12 @@ namespace gbe
 
     // Generate the MOV instruction and replace the register in the instruction
     SelectionInstruction *mov = this->create(SEL_OP_MOV, 1, 1);
-    mov->dst(0) = GenRegister::retype(insn->dst(regID), genType);
+    mov->dst(0) = dst;
     mov->state = GenInstructionState(simdWidth);
     if (simdWidth == 1)
       mov->state.noMask = 1;
     gr = f == ir::FAMILY_QWORD ? GenRegister::dfxgrf(simdWidth, tmp) : GenRegister::fxgrf(simdWidth, tmp);
-    insn->dst(regID) = mov->src(0) = gr;
+    insn->dst(regID) = mov->src(0) = GenRegister::retype(gr, dst.type);
     insn->append(*mov);
     return tmp;
   }
-- 
1.7.10.4