[Beignet] [PATCH 1/2] GBE: refine disassembly code to show null register's type.
Song, Ruiling
ruiling.song at intel.com
Fri May 23 00:33:08 PDT 2014
LGTM
-----Original Message-----
From: Beignet [mailto:beignet-bounces at lists.freedesktop.org] On Behalf Of Zhigang Gong
Sent: Monday, May 19, 2014 12:33 PM
To: beignet at lists.freedesktop.org
Cc: Gong, Zhigang
Subject: [Beignet] [PATCH 1/2] GBE: refine disassembly code to show null register's type.
We should show null register's type in the assembly output, as if a null reigster is using a wrong type, such as the following
instruction:
cmp.le(8) null:UW g2<8,8,1>:F 0.1F
It is a fatal error from the hardware point of view. We should output that information.
Signed-off-by: Zhigang Gong <zhigang.gong at intel.com>
---
backend/src/backend/gen/gen_mesa_disasm.c | 20 +++++++++++---------
1 file changed, 11 insertions(+), 9 deletions(-)
diff --git a/backend/src/backend/gen/gen_mesa_disasm.c b/backend/src/backend/gen/gen_mesa_disasm.c
index 871277b..81c33a6 100644
--- a/backend/src/backend/gen/gen_mesa_disasm.c
+++ b/backend/src/backend/gen/gen_mesa_disasm.c
@@ -254,14 +254,14 @@ static const char *access_mode[2] = { };
static const char *reg_encoding[8] = {
- [0] = "UD",
- [1] = "D",
- [2] = "UW",
- [3] = "W",
- [4] = "UB",
- [5] = "B",
- [6] = "DF",
- [7] = "F"
+ [0] = ":UD",
+ [1] = ":D",
+ [2] = ":UW",
+ [3] = ":W",
+ [4] = ":UB",
+ [5] = ":B",
+ [6] = ":DF",
+ [7] = ":F"
};
int reg_type_size[8] = {
@@ -542,8 +542,10 @@ static int dest (FILE *file, const union GenNativeInstruction *inst)
if (inst->bits1.da1.dest_address_mode == GEN_ADDRESS_DIRECT)
{
err |= reg (file, inst->bits1.da1.dest_reg_file, inst->bits1.da1.dest_reg_nr);
- if (err == -1)
+ if (err == -1) {
+ control (file, "dest reg encoding", reg_encoding,
+ inst->bits1.da1.dest_reg_type, NULL);
return 0;
+ }
if (inst->bits1.da1.dest_subreg_nr)
format (file, ".%d", inst->bits1.da1.dest_subreg_nr /
reg_type_size[inst->bits1.da1.dest_reg_type]);
--
1.8.3.2
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