[Beignet] [PATCH 2/4] GBE: further optimize vector mov.

[Zhigang Gong]

This patch could handle two different vectors which are not share the first element.
For example,

%10, %99, %13   : v0
%11, %100, %13  : v1

If the %10 and %11, %99 and %100 are not interefering each other, we can
make them share the same physical vector.

Signed-off-by: Zhigang Gong <zhigang.gong at intel.com>
---
 backend/src/backend/gen_reg_allocation.cpp | 36 +++++++++++++++++++++---------
 1 file changed, 25 insertions(+), 11 deletions(-)

diff --git a/backend/src/backend/gen_reg_allocation.cpp b/backend/src/backend/gen_reg_allocation.cpp
index 9facfca..f53796a 100644
--- a/backend/src/backend/gen_reg_allocation.cpp
+++ b/backend/src/backend/gen_reg_allocation.cpp
@@ -265,8 +265,6 @@ namespace gbe
   }
 
   bool GenRegAllocator::Opaque::isAllocated(const SelectionVector *vector) {
-    const ir::Register first = vector->reg[0].reg();
-    const auto it = vectorMap.find(first);
 
     // If the first register is not allocated we are done
     // FIXME, even if first register is not allocated, we still have some chance to
@@ -276,21 +274,37 @@ namespace gbe
     //  {%22, %12, %13, %14} current vector.
     // If %22 and %10 have no interference with each other, we can make a proxy pair
     // here and save 3 extra MOV here.
-    if (it == vectorMap.end())
-      return false;
+    uint32_t otherFirst = 0;
+    uint32_t matchedID = INT_MAX;
+    SelectionVector *other = NULL;
+    for (uint32_t regID = 0; regID < vector->regNum; ++regID) {
 
-    // If there are more left registers than in the found vector, there are
-    // still registers to allocate
-    const SelectionVector *other = it->second.first;
-    const uint32_t otherFirst = it->second.second;
-    const uint32_t leftNum = other->regNum - otherFirst;
-    if (leftNum < vector->regNum)
+      const ir::Register reg = vector->reg[regID].reg();
+      auto it = vectorMap.find(reg);
+      if (it != vectorMap.end()) {
+        other = it->second.first;
+        const uint32_t otherRegID = it->second.second;
+        // If there are more left registers than in the found vector, there are
+        // still registers to allocate
+        if (otherRegID < regID)
+          return false;
+        if (other->regNum - otherRegID < vector->regNum - regID)
+          return false;
+        otherFirst = otherRegID - regID;
+        matchedID = regID;
+        break;
+      }
+    }
+    if (matchedID == INT_MAX)
       return false;
 
+
     // Now check that all the registers in the already allocated vector match
     // the current vector
     map<ir::Register, ir::Register> tmpProxyRegMap;
-    for (uint32_t regID = 1; regID < vector->regNum; ++regID) {
+    for (uint32_t regID = 0; regID < vector->regNum; ++regID) {
+       if (regID == matchedID)
+         continue;
        const ir::Register from = vector->reg[regID].reg();
        const ir::Register to = other->reg[regID + otherFirst].reg();
        if (from == to)
-- 
1.8.3.2