[Beignet] [PATCH] BDW: Change the default tiling mode to TILING_Y on BDW.

[Yang Rong]

TILING_Y's performance is better than TILING_X'S on BDW, but almost same
on IVB/HSW. Using the TILING_Y as default tiling mode temporary, still need
to find out the root cause why different behavior between BDW and IVB/HSW.

Signed-off-by: Yang Rong <rong.r.yang at intel.com>
---
 src/cl_mem.c | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/src/cl_mem.c b/src/cl_mem.c
index d319966..84e3928 100644
--- a/src/cl_mem.c
+++ b/src/cl_mem.c
@@ -637,10 +637,14 @@ cl_mem_copy_image(struct _cl_mem_image *image,
   cl_mem_unmap_auto((cl_mem)image);
 }
 
-cl_image_tiling_t cl_get_default_tiling(void)
+cl_image_tiling_t cl_get_default_tiling(cl_driver drv)
 {
   static int initialized = 0;
-  static cl_image_tiling_t tiling = CL_TILE_X;
+  cl_image_tiling_t tiling = CL_TILE_X;
+
+  // FIXME, need to find out the performance diff's root cause on BDW.
+  if(cl_driver_get_ver(drv) == 8)
+    tiling = CL_TILE_Y;
   if (!initialized) {
     char *tilingStr = getenv("OCL_TILING");
     if (tilingStr != NULL) {
@@ -733,7 +737,7 @@ _cl_mem_new_image(cl_context ctx,
 
     /* Pick up tiling mode (we do only linear on SNB) */
     if (cl_driver_get_ver(ctx->drv) != 6)
-      tiling = cl_get_default_tiling();
+      tiling = cl_get_default_tiling(ctx->drv);
 
     depth = 1;
   } else if (image_type == CL_MEM_OBJECT_IMAGE3D ||
@@ -743,7 +747,7 @@ _cl_mem_new_image(cl_context ctx,
       h = 1;
       tiling = CL_NO_TILE;
     } else if (cl_driver_get_ver(ctx->drv) != 6)
-      tiling = cl_get_default_tiling();
+      tiling = cl_get_default_tiling(ctx->drv);
 
     size_t min_pitch = bpp * w;
     if (data && pitch == 0)
-- 
1.8.3.2