[Beignet] [PATCH] Change the IVB/HSW L3 SQC credit setting.

[Zhigang Gong]

This patch LGTM, will push to master branch.
Thanks.

On Mon, Nov 17, 2014 at 11:08:20AM +0800, Yang Rong wrote:
> Set the L3SQ General Priority Credit to max, and L3SQ High Priority Credit
> to zero, it can slightly improve the performacne, about 2% of luxmark.
> 
> Signed-off-by: Yang Rong <rong.r.yang at intel.com>
> ---
>  src/intel/intel_gpgpu.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/src/intel/intel_gpgpu.c b/src/intel/intel_gpgpu.c
> index b6e19db..ffe382c 100644
> --- a/src/intel/intel_gpgpu.c
> +++ b/src/intel/intel_gpgpu.c
> @@ -566,7 +566,7 @@ intel_gpgpu_set_L3_gen7(intel_gpgpu_t *gpgpu, uint32_t use_slm)
>    BEGIN_BATCH(gpgpu->batch, 9);
>    OUT_BATCH(gpgpu->batch, CMD_LOAD_REGISTER_IMM | 1); /* length - 2 */
>    OUT_BATCH(gpgpu->batch, GEN7_L3_SQC_REG1_ADDRESS_OFFSET);
> -  OUT_BATCH(gpgpu->batch, 0x00730000);
> +  OUT_BATCH(gpgpu->batch, 0x00A00000);
>  
>    OUT_BATCH(gpgpu->batch, CMD_LOAD_REGISTER_IMM | 1); /* length - 2 */
>    OUT_BATCH(gpgpu->batch, GEN7_L3_CNTL_REG2_ADDRESS_OFFSET);
> @@ -619,7 +619,7 @@ intel_gpgpu_set_L3_gen75(intel_gpgpu_t *gpgpu, uint32_t use_slm)
>    BEGIN_BATCH(gpgpu->batch, 9);
>    OUT_BATCH(gpgpu->batch, CMD_LOAD_REGISTER_IMM | 1); /* length - 2 */
>    OUT_BATCH(gpgpu->batch, GEN7_L3_SQC_REG1_ADDRESS_OFFSET);
> -  OUT_BATCH(gpgpu->batch, 0x00610000);
> +  OUT_BATCH(gpgpu->batch, 0x00800000);
>  
>    OUT_BATCH(gpgpu->batch, CMD_LOAD_REGISTER_IMM | 1); /* length - 2 */
>    OUT_BATCH(gpgpu->batch, GEN7_L3_CNTL_REG2_ADDRESS_OFFSET);
> -- 
> 1.8.3.2
> 
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