[Beignet] [PATCH 1/3] GBE: Fix a bug when setting flag register
Ruiling Song
ruiling.song at intel.com
Fri Oct 10 00:01:25 PDT 2014
we should use simd1, instead of simd8/simd16.
Signed-off-by: Ruiling Song <ruiling.song at intel.com>
---
backend/src/backend/gen_context.cpp | 20 ++++++++++++++------
backend/src/backend/gen_context.hpp | 1 +
2 files changed, 15 insertions(+), 6 deletions(-)
diff --git a/backend/src/backend/gen_context.cpp b/backend/src/backend/gen_context.cpp
index 8844233..245c318 100644
--- a/backend/src/backend/gen_context.cpp
+++ b/backend/src/backend/gen_context.cpp
@@ -763,14 +763,14 @@ namespace gbe
p->SHL(c, e, a);
p->SHL(d, f, a);
p->OR(e, d, b);
- p->MOV(flagReg, GenRegister::immuw(0xFFFF));
+ setFlag(flagReg, GenRegister::immuw(0xFFFF));
p->curr.predicate = GEN_PREDICATE_NORMAL;
p->curr.useFlag(flagReg.flag_nr(), flagReg.flag_subnr());
p->CMP(GEN_CONDITIONAL_Z, a, zero);
p->SEL(d, d, e);
p->curr.predicate = GEN_PREDICATE_NONE;
p->AND(a, a, GenRegister::immud(32));
- p->MOV(flagReg, GenRegister::immuw(0xFFFF));
+ setFlag(flagReg, GenRegister::immuw(0xFFFF));
p->curr.predicate = GEN_PREDICATE_NORMAL;
p->curr.useFlag(flagReg.flag_nr(), flagReg.flag_subnr());
p->CMP(GEN_CONDITIONAL_Z, a, zero);
@@ -791,14 +791,14 @@ namespace gbe
p->SHR(c, f, a);
p->SHR(d, e, a);
p->OR(e, d, b);
- p->MOV(flagReg, GenRegister::immuw(0xFFFF));
+ setFlag(flagReg, GenRegister::immuw(0xFFFF));
p->curr.predicate = GEN_PREDICATE_NORMAL;
p->curr.useFlag(flagReg.flag_nr(), flagReg.flag_subnr());
p->CMP(GEN_CONDITIONAL_Z, a, zero);
p->SEL(d, d, e);
p->curr.predicate = GEN_PREDICATE_NONE;
p->AND(a, a, GenRegister::immud(32));
- p->MOV(flagReg, GenRegister::immuw(0xFFFF));
+ setFlag(flagReg, GenRegister::immuw(0xFFFF));
p->curr.predicate = GEN_PREDICATE_NORMAL;
p->curr.useFlag(flagReg.flag_nr(), flagReg.flag_subnr());
p->CMP(GEN_CONDITIONAL_Z, a, zero);
@@ -820,7 +820,7 @@ namespace gbe
p->ASR(c, f, a);
p->SHR(d, e, a);
p->OR(e, d, b);
- p->MOV(flagReg, GenRegister::immuw(0xFFFF));
+ setFlag(flagReg, GenRegister::immuw(0xFFFF));
p->curr.predicate = GEN_PREDICATE_NORMAL;
p->curr.useFlag(flagReg.flag_nr(), flagReg.flag_subnr());
p->CMP(GEN_CONDITIONAL_Z, a, zero);
@@ -828,7 +828,7 @@ namespace gbe
p->curr.predicate = GEN_PREDICATE_NONE;
p->AND(a, a, GenRegister::immud(32));
p->ASR(f, f, GenRegister::immd(31));
- p->MOV(flagReg, GenRegister::immuw(0xFFFF));
+ setFlag(flagReg, GenRegister::immuw(0xFFFF));
p->curr.predicate = GEN_PREDICATE_NORMAL;
p->curr.useFlag(flagReg.flag_nr(), flagReg.flag_subnr());
p->CMP(GEN_CONDITIONAL_Z, a, zero);
@@ -842,6 +842,14 @@ namespace gbe
NOT_IMPLEMENTED;
}
}
+ void GenContext::setFlag(GenRegister flagReg, GenRegister src) {
+ p->push();
+ p->curr.noMask = 1;
+ p->curr.execWidth = 1;
+ p->curr.predicate = GEN_PREDICATE_NONE;
+ p->MOV(flagReg, src);
+ p->pop();
+ }
void GenContext::saveFlag(GenRegister dest, int flag, int subFlag) {
p->push();
diff --git a/backend/src/backend/gen_context.hpp b/backend/src/backend/gen_context.hpp
index 4a01fd5..7a51f57 100644
--- a/backend/src/backend/gen_context.hpp
+++ b/backend/src/backend/gen_context.hpp
@@ -116,6 +116,7 @@ namespace gbe
void I64FullAdd(GenRegister high1, GenRegister low1, GenRegister high2, GenRegister low2);
void I32FullMult(GenRegister high, GenRegister low, GenRegister src0, GenRegister src1);
void I64FullMult(GenRegister dst1, GenRegister dst2, GenRegister dst3, GenRegister dst4, GenRegister x_high, GenRegister x_low, GenRegister y_high, GenRegister y_low);
+ void setFlag(GenRegister flag, GenRegister src);
void saveFlag(GenRegister dest, int flag, int subFlag);
void UnsignedI64ToFloat(GenRegister dst, GenRegister high, GenRegister low, GenRegister exp, GenRegister mantissa, GenRegister tmp, GenRegister flag);
--
1.7.10.4
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