[Beignet] [PATCH] BDW: Fix bwd 32*32 scalar multiplication bug.

[Zhigang Gong]

LGTM, will push latter. Thanks.

On Wed, Oct 29, 2014 at 03:37:38PM +0800, Yang Rong wrote:
> When scalar multiplication, must disable predicate and don't need specail handle.
> 
> Signed-off-by: Yang Rong <rong.r.yang at intel.com>
> ---
>  backend/src/backend/gen_insn_selection.cpp | 10 ++++------
>  1 file changed, 4 insertions(+), 6 deletions(-)
> 
> diff --git a/backend/src/backend/gen_insn_selection.cpp b/backend/src/backend/gen_insn_selection.cpp
> index 605fdd5..64e9fd8 100644
> --- a/backend/src/backend/gen_insn_selection.cpp
> +++ b/backend/src/backend/gen_insn_selection.cpp
> @@ -2566,14 +2566,12 @@ namespace gbe
>  
>        sel.push();
>        if (sel.has32X32Mul()) {
> -        //Seems scalar mul need QWROD dst, otherwise will touch the dst's follow register.
>          if (sel.isScalarReg(insn.getDst(0)) == true) {
>            sel.curr.execWidth = 1;
> -          GenRegister tmp = sel.selReg(sel.reg(FAMILY_QWORD), Type::TYPE_S64);
> -          sel.MUL(tmp, src0, src1);
> -          sel.MOV(dst, GenRegister::retype(tmp, GEN_TYPE_D));
> -        } else
> -          sel.MUL(dst, src0, src1);
> +          sel.curr.predicate = GEN_PREDICATE_NONE;
> +          sel.curr.noMask = 1;
> +        }
> +        sel.MUL(dst, src0, src1);
>        } else {
>          if (sel.isScalarReg(insn.getDst(0)) == true) {
>            sel.curr.execWidth = 1;
> -- 
> 1.9.1
> 
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