[Beignet] [PATCH 1/3] Add Gen IR WHILE.

[xionghu.luo at intel.com]

From: Luo Xionghu <xionghu.luo at intel.com>

Add Gen IR WHILE to mark the strucutred region.

Signed-off-by: Luo Xionghu <xionghu.luo at intel.com>
---
 backend/src/ir/instruction.cpp |    7 ++++++-
 backend/src/ir/instruction.hpp |    2 ++
 backend/src/ir/instruction.hxx |    1 +
 3 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/backend/src/ir/instruction.cpp b/backend/src/ir/instruction.cpp
index 370fb87..b8beea1 100644
--- a/backend/src/ir/instruction.cpp
+++ b/backend/src/ir/instruction.cpp
@@ -349,7 +349,7 @@ namespace ir {
     {
     public:
       INLINE BranchInstruction(Opcode op, LabelIndex labelIndex, Register predicate, bool inv_pred=false) {
-        GBE_ASSERT(op == OP_BRA || op == OP_IF);
+        GBE_ASSERT(op == OP_BRA || op == OP_IF || op == OP_WHILE);
         this->opcode = op;
         this->predicate = predicate;
         this->labelIndex = labelIndex;
@@ -1634,6 +1634,11 @@ DECL_MEM_FN(GetImageInfoInstruction, uint8_t, getImageIndex(void), getImageIndex
     return internal::BranchInstruction(OP_ENDIF, labelIndex).convert();
   }
 
+  // WHILE
+  Instruction WHILE(LabelIndex labelIndex, Register pred) {
+    return internal::BranchInstruction(OP_WHILE, labelIndex, pred).convert();
+  }
+
   // RET
   Instruction RET(void) {
     return internal::BranchInstruction(OP_RET).convert();
diff --git a/backend/src/ir/instruction.hpp b/backend/src/ir/instruction.hpp
index 39fb2db..afaedff 100644
--- a/backend/src/ir/instruction.hpp
+++ b/backend/src/ir/instruction.hpp
@@ -670,6 +670,8 @@ namespace ir {
   Instruction ELSE(LabelIndex labelIndex);
   /*! endif */
   Instruction ENDIF(LabelIndex labelIndex);
+  /*! (pred) while labelIndex */
+  Instruction WHILE(LabelIndex labelIndex, Register pred);
   /*! ret */
   Instruction RET(void);
   /*! load.type.space {dst1,...,dst_valueNum} offset value */
diff --git a/backend/src/ir/instruction.hxx b/backend/src/ir/instruction.hxx
index abc984f..f86d0e1 100644
--- a/backend/src/ir/instruction.hxx
+++ b/backend/src/ir/instruction.hxx
@@ -96,3 +96,4 @@ DECL_INSN(MAD, TernaryInstruction)
 DECL_INSN(IF, BranchInstruction)
 DECL_INSN(ENDIF, BranchInstruction)
 DECL_INSN(ELSE, BranchInstruction)
+DECL_INSN(WHILE, BranchInstruction)
-- 
1.7.9.5