[Beignet] [PATCH V2 0/5] Prepare to enable identify structurized loop block.

[Zhigang Gong]

This is version 2 based on xionghu's first version. Major modifications are
as below:

1. Fixed one bug in the loop analysis. We are close to fully enable this feature.
   But still disable it by default as there are a few regressions even with this
   patchset, please see commit log of the last patch for details.
2. Add "while" handling in HSW backend.

Luo Xionghu (3):
  Add Gen IR WHILE.
  add handleSelfLoopNode to insert while instruction on Gen IR level.
  Use instruction WHILE to manipulate structure.

Zhigang Gong (2):
  GBE: fix a loop header file including bug.
  GBE: structurized loop exit need an extra branching instruction when
    do reordering.

 backend/src/backend/gen75_encoder.cpp       | 22 +++++++----
 backend/src/backend/gen_context.cpp         | 10 +++++
 backend/src/backend/gen_encoder.cpp         | 13 ++++++-
 backend/src/backend/gen_encoder.hpp         |  2 +
 backend/src/backend/gen_insn_scheduling.cpp |  2 +-
 backend/src/backend/gen_insn_selection.cpp  | 20 ++++++++++
 backend/src/backend/gen_insn_selection.hxx  |  1 +
 backend/src/ir/function.cpp                 | 19 ++++++++--
 backend/src/ir/function.hpp                 |  9 ++++-
 backend/src/ir/instruction.cpp              |  7 +++-
 backend/src/ir/instruction.hpp              |  2 +
 backend/src/ir/instruction.hxx              |  1 +
 backend/src/ir/structural_analysis.cpp      | 59 ++++++++++++++++++++++-------
 backend/src/ir/structural_analysis.hpp      |  4 +-
 14 files changed, 141 insertions(+), 30 deletions(-)

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1.8.3.2