[Beignet] [PATCH 4/6] BDW: Add function intel_gpgpu_setup_bti for gen8.

[Yang Rong]

From: Junyan He <junyan.he at linux.intel.com>

Also set the correct surface cache control.

Signed-off-by: Junyan He <junyan.he at linux.intel.com>
---
 src/cl_driver.h         | 16 ++++++++++++++++
 src/intel/intel_gpgpu.c | 39 +++++++++++++++++++++++++++++++++++++++
 2 files changed, 55 insertions(+)

diff --git a/src/cl_driver.h b/src/cl_driver.h
index 38b4830..e973ba5 100644
--- a/src/cl_driver.h
+++ b/src/cl_driver.h
@@ -81,6 +81,22 @@ typedef enum cl_llccc_cache_control {
   llccc_ucllc    = 0x3<<1
 } cl_llccc_cache_control;
 
+/* Target Cache control options for gen8 */
+typedef enum cl_target_cache_control {
+  tcc_ec_only    = 0x0<<3,
+  tcc_llc_only   = 0x1<<3,
+  tcc_llc_ec     = 0x2<<3,
+  tcc_llc_ec_l3  = 0x3<<3
+} cl_target_cache_control;
+
+/* Memory type LLC/ELLC Cache control options for gen8 */
+typedef enum cl_mtllc_cache_control {
+  mtllc_pte      = 0x0<<5,
+  mtllc_none     = 0x1<<5,
+  mtllc_wt       = 0x2<<5,
+  mtllc_wb       = 0x3<<5
+} cl_mtllc_cache_control;
+
 typedef enum gpu_command_status {
   command_queued    = 3,
   command_submitted = 2,
diff --git a/src/intel/intel_gpgpu.c b/src/intel/intel_gpgpu.c
index c4b9156..63d44e7 100644
--- a/src/intel/intel_gpgpu.c
+++ b/src/intel/intel_gpgpu.c
@@ -61,6 +61,13 @@ typedef struct surface_heap {
   char surface[256][sizeof(gen6_surface_state_t)];
 } surface_heap_t;
 
+/* Stores both binding tables and surface states */
+typedef struct surface_heap_gen8 {
+  uint32_t binding_table[256];
+  char surface[256][sizeof(gen8_surface_state_t)];
+} surface_heap_gen8_t;
+
+
 typedef struct intel_event {
   drm_intel_bo *buffer;
   drm_intel_bo *ts_buf;
@@ -220,6 +227,11 @@ intel_gpgpu_get_cache_ctrl_gen75()
 {
   return llccc_ec | l3cc_ec;
 }
+static uint32_t
+intel_gpgpu_get_cache_ctrl_gen8()
+{
+  return tcc_llc_ec_l3 | mtllc_wb;
+}
 
 static void
 intel_gpgpu_set_base_address(intel_gpgpu_t *gpgpu)
@@ -787,6 +799,33 @@ intel_gpgpu_setup_bti(intel_gpgpu_t *gpgpu, drm_intel_bo *buf, uint32_t internal
                       buf);
 }
 
+static void
+intel_gpgpu_setup_bti_gen8(intel_gpgpu_t *gpgpu, drm_intel_bo *buf,
+                           uint32_t internal_offset, uint32_t size, unsigned char index)
+{
+  uint32_t s = size - 1;
+  surface_heap_gen8_t *heap = gpgpu->aux_buf.bo->virtual + gpgpu->aux_offset.surface_heap_offset;
+  gen8_surface_state_t *ss0 = (gen8_surface_state_t *) heap->surface[index];
+  memset(ss0, 0, sizeof(gen8_surface_state_t));
+  ss0->ss0.surface_type = I965_SURFACE_BUFFER;
+  ss0->ss0.surface_format = I965_SURFACEFORMAT_RAW;
+  ss0->ss2.width  = s & 0x7f;   /* bits 6:0 of sz */
+  assert(ss0->ss2.width & 0x03);
+  ss0->ss2.height = (s >> 7) & 0x3fff; /* bits 20:7 of sz */
+  ss0->ss3.depth  = (s >> 21) & 0x3ff; /* bits 30:21 of sz */
+  ss0->ss1.mem_obj_ctrl_state = cl_gpgpu_get_cache_ctrl();
+  heap->binding_table[index] = offsetof(surface_heap_t, surface) + index * sizeof(gen8_surface_state_t);
+// TODO:
+//  ss0->ss1.base_addr = buf->offset + internal_offset;
+  dri_bo_emit_reloc(gpgpu->aux_buf.bo,
+                      I915_GEM_DOMAIN_RENDER,
+                      I915_GEM_DOMAIN_RENDER,
+                      internal_offset,
+                      gpgpu->aux_offset.surface_heap_offset +
+                      heap->binding_table[index] +
+                      offsetof(gen7_surface_state_t, ss1),
+                      buf);
+}
 
 static int
 intel_is_surface_array(cl_mem_object_type type)
-- 
1.8.3.2