[Beignet] [PATCH 08/13] Backend: Add state register into schedule consideration.
Yang, Rong R
rong.r.yang at intel.com
Wed Dec 9 00:16:50 PST 2015
> -----Original Message-----
> From: Beignet [mailto:beignet-bounces at lists.freedesktop.org] On Behalf Of
> junyan.he at inbox.com
> Sent: Tuesday, December 1, 2015 16:11
> To: beignet at lists.freedesktop.org
> Subject: [Beignet] [PATCH 08/13] Backend: Add state register into schedule
> consideration.
>
> From: Junyan He <junyan.he at linux.intel.com>
>
> Because the workgroup OP has forwarding msg and wait functions, it needs
> all the threads to sync with each other. It has very similar behavior as
> BARRIER, so we add it into schedule consideration accordingly.
>
> Signed-off-by: Junyan He <junyan.he at linux.intel.com>
> ---
> backend/src/backend/gen_insn_scheduling.cpp | 16 ++++++++++++----
> 1 file changed, 12 insertions(+), 4 deletions(-)
>
> diff --git a/backend/src/backend/gen_insn_scheduling.cpp
> b/backend/src/backend/gen_insn_scheduling.cpp
> index 8111e0c..710194e 100644
> --- a/backend/src/backend/gen_insn_scheduling.cpp
> +++ b/backend/src/backend/gen_insn_scheduling.cpp
> @@ -192,8 +192,10 @@ namespace gbe
> static const uint32_t MAX_ACC_REGISTER = 1u;
> /*! Maximum number of *physical* tm registers */
> static const uint32_t MAX_TM_REGISTER = 1u;
> + /*! Maximum number of state registers */
> + static const uint32_t MAX_ST_REGISTER = 2u;
> /*! Maximum number of *physical* arf registers */
> - static const uint32_t MAX_ARF_REGISTER = MAX_FLAG_REGISTER +
> MAX_ACC_REGISTER + MAX_TM_REGISTER;
> + static const uint32_t MAX_ARF_REGISTER = MAX_FLAG_REGISTER +
> + MAX_ACC_REGISTER + MAX_TM_REGISTER + MAX_TM_REGISTER;
Typo, MAX_ST_REGISTER?
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