[Beignet] [PATCH 2/2] [OCL20] fix debug instruction welform assert.
xionghu.luo at intel.com
xionghu.luo at intel.com
Thu Dec 10 19:22:09 PST 2015
From: Luo Xionghu <xionghu.luo at intel.com>
handle llvm.fabs.f16 instruction in case compiler_half_isnan.
Signed-off-by: Luo Xionghu <xionghu.luo at intel.com>
---
backend/src/llvm/llvm_gen_backend.cpp | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/backend/src/llvm/llvm_gen_backend.cpp b/backend/src/llvm/llvm_gen_backend.cpp
index df949d0..cb47097 100644
--- a/backend/src/llvm/llvm_gen_backend.cpp
+++ b/backend/src/llvm/llvm_gen_backend.cpp
@@ -3883,7 +3883,6 @@ namespace gbe
break;
case Intrinsic::sqrt: this->emitUnaryCallInst(I,CS,ir::OP_SQR); break;
case Intrinsic::ceil: this->emitUnaryCallInst(I,CS,ir::OP_RNDU); break;
- case Intrinsic::fabs: this->emitUnaryCallInst(I,CS,ir::OP_ABS); break;
case Intrinsic::trunc: this->emitUnaryCallInst(I,CS,ir::OP_RNDZ); break;
case Intrinsic::rint: this->emitUnaryCallInst(I,CS,ir::OP_RNDE); break;
case Intrinsic::floor: this->emitUnaryCallInst(I,CS,ir::OP_RNDD); break;
@@ -3901,6 +3900,13 @@ namespace gbe
ctx.POW(ir::TYPE_FLOAT, dst, src0, src1);
break;
}
+ case Intrinsic::fabs:
+ {
+ const ir::Register src = this->getRegister(*AI);
+ const ir::Register dst = this->getRegister(&I);
+ ctx.ALU1(ir::OP_ABS, getType(ctx, (*AI)->getType()), dst, src);
+ break;
+ }
default: NOT_IMPLEMENTED;
}
} else {
--
2.1.4
More information about the Beignet
mailing list