[Beignet] [PATCH] fix a bug when the first operand of intel_sub_group_shuffle is uniform

[Guo Yejun]

actually, if the first operand is uniform, no matter what the second
operand is, the result is always the same value of the first operand.

Signed-off-by: Guo Yejun <yejun.guo at intel.com>
---
 backend/src/backend/gen_insn_selection.cpp | 38 +++++++++++++++++-------------
 1 file changed, 21 insertions(+), 17 deletions(-)

diff --git a/backend/src/backend/gen_insn_selection.cpp b/backend/src/backend/gen_insn_selection.cpp
index 630f5bc..001a3c5 100644
--- a/backend/src/backend/gen_insn_selection.cpp
+++ b/backend/src/backend/gen_insn_selection.cpp
@@ -5659,23 +5659,27 @@ extern bool OCL_DEBUGINFO; // first defined by calling BVAR in program.cpp
       }
 
       sel.push();
-      if (sel.isScalarReg(insn.getDst(0))) {
-        sel.curr.execWidth = 1;
-        sel.curr.predicate = GEN_PREDICATE_NONE;
-        sel.curr.noMask = 1;
-      }
-      if (src1.file == GEN_IMMEDIATE_VALUE) {
-        uint32_t offset = src1.value.ud % sel.curr.execWidth;
-        GenRegister reg = GenRegister::subphysicaloffset(src0, offset);
-        reg.vstride = GEN_VERTICAL_STRIDE_0;
-        reg.hstride = GEN_HORIZONTAL_STRIDE_0;
-        reg.width = GEN_WIDTH_1;
-        sel.MOV(dst, reg);
-      }
-      else {
-        GenRegister shiftL = sel.selReg(sel.reg(FAMILY_DWORD), TYPE_U32);
-        sel.SHL(shiftL, src1, GenRegister::immud(0x2));
-        sel.SIMD_SHUFFLE(dst, src0, shiftL);
+      if (sel.isScalarReg(insn.getSrc(0))) {
+        if (sel.isScalarReg(insn.getDst(0))) {
+          sel.curr.execWidth = 1;
+          sel.curr.predicate = GEN_PREDICATE_NONE;
+          sel.curr.noMask = 1;
+        }
+        sel.MOV(dst, src0);     //no matter what src1 is
+      } else {
+        if (src1.file == GEN_IMMEDIATE_VALUE) {
+          uint32_t offset = src1.value.ud % sel.curr.execWidth;
+          GenRegister reg = GenRegister::subphysicaloffset(src0, offset);
+          reg.vstride = GEN_VERTICAL_STRIDE_0;
+          reg.hstride = GEN_HORIZONTAL_STRIDE_0;
+          reg.width = GEN_WIDTH_1;
+          sel.MOV(dst, reg);
+        }
+        else {
+          GenRegister shiftL = sel.selReg(sel.reg(FAMILY_DWORD), TYPE_U32);
+          sel.SHL(shiftL, src1, GenRegister::immud(0x2));
+          sel.SIMD_SHUFFLE(dst, src0, shiftL);
+        }
       }
       sel.pop();
       return true;
-- 
1.9.1