[Beignet] [PATCH 15/18] Backend: Fix two bugs for Gen context.

[junyan.he at inbox.com]

From: Junyan He <junyan.he at linux.intel.com>

1. The state register should be <0,1,0>
2. Place the prolog logic after generating bool 0,1 to
   get more precise timestamp.

Signed-off-by: Junyan He <junyan.he at linux.intel.com>
---
 backend/src/backend/gen_context.cpp  | 7 +++----
 backend/src/backend/gen_register.hpp | 4 ++--
 2 files changed, 5 insertions(+), 6 deletions(-)

diff --git a/backend/src/backend/gen_context.cpp b/backend/src/backend/gen_context.cpp
index 6edad4f..0624497 100644
--- a/backend/src/backend/gen_context.cpp
+++ b/backend/src/backend/gen_context.cpp
@@ -2584,7 +2584,6 @@ namespace gbe
     uint32_t tsType = insn.extra.timestampType;
     GenRegister flagReg = GenRegister::flag(insn.state.flag, insn.state.subFlag);
 
-    GBE_ASSERT(tsType == 1);
     GenRegister tmArf = GenRegister::tm0();
     GenRegister profilingReg[5];
     GenRegister tmp;
@@ -2709,7 +2708,6 @@ namespace gbe
     GenRegister tmp = ra->genReg(insn.dst(0));
     uint32_t profilingType = insn.extra.profilingType;
     uint32_t bti = insn.extra.profilingBTI;
-    GBE_ASSERT(profilingType == 1);
     GenRegister flagReg = GenRegister::flag(insn.state.flag, insn.state.subFlag);
     GenRegister lastTsReg = GenRegister::toUniform(profilingReg[3], GEN_TYPE_UL);
     lastTsReg = GenRegister::offset(lastTsReg, 0, 2*sizeof(uint64_t));
@@ -2810,6 +2808,7 @@ namespace gbe
       GenRegister ffid = GenRegister::toUniform(data, GEN_TYPE_UD);
       GenRegister tmp = GenRegister::toUniform(profilingReg[3], GEN_TYPE_UD);
       GenRegister stateReg =  GenRegister::sr(0, 0);
+      p->curr.predicate = GEN_PREDICATE_NONE;
       p->curr.noMask = 1;
       p->curr.execWidth = 1;
       p->MOV(ffid, stateReg);
@@ -3201,11 +3200,11 @@ do { \
     schedulePostRegAllocation(*this, *this->sel);
     if (OCL_OUTPUT_REG_ALLOC)
       ra->outputAllocation();
+    this->emitStackPointer();
+    this->clearFlagRegister();
     if (inProfilingMode) { // add the profiling prolog before do anything.
       this->profilingProlog();
     }
-    this->emitStackPointer();
-    this->clearFlagRegister();
     this->emitSLMOffset();
     this->emitInstructionStream();
     if (this->patchBranches() == false)
diff --git a/backend/src/backend/gen_register.hpp b/backend/src/backend/gen_register.hpp
index aa0744b..ee3b570 100644
--- a/backend/src/backend/gen_register.hpp
+++ b/backend/src/backend/gen_register.hpp
@@ -833,8 +833,8 @@ namespace gbe
                          GEN_ARF_STATE | nr,
                          subnr,
                          GEN_TYPE_UD,
-                         GEN_VERTICAL_STRIDE_8,
-                         GEN_WIDTH_8,
+                         GEN_VERTICAL_STRIDE_0,
+                         GEN_WIDTH_1,
                          GEN_HORIZONTAL_STRIDE_1);
     }
 
-- 
1.9.1