[Beignet] [PATCH] considering width and hstride when do unpacked_uw

[Song, Ruiling]

Thanks for the fix. And the patch is OK for me.
And we still have lots of places to be modified in GenContext.
I think we can push the patch, and fix other remaining places in next patch.
And the unpacked_uw() seems not quite proper anymore. We need another better name for it.

Thanks!
Ruiling

> -----Original Message-----
> From: Beignet [mailto:beignet-bounces at lists.freedesktop.org] On Behalf Of
> Guo Yejun
> Sent: Monday, December 21, 2015 9:28 AM
> To: beignet at lists.freedesktop.org
> Cc: Guo, Yejun <yejun.guo at intel.com>
> Subject: [Beignet] [PATCH] considering width and hstride when do
> unpacked_uw
> 
> the current code assumes the original register is <8,8,1>:UD, it is
> no longer true with the selection ir optimization, so, add a new function
> to do unpacked_uw with consideration of width and hstride of original
> register.
> 
> Signed-off-by: Guo Yejun <yejun.guo at intel.com>
> ---
>  backend/src/backend/gen_context.cpp  |  2 +-
>  backend/src/backend/gen_register.hpp | 26
> ++++++++++++++++++++++++++
>  2 files changed, 27 insertions(+), 1 deletion(-)
> 
> diff --git a/backend/src/backend/gen_context.cpp
> b/backend/src/backend/gen_context.cpp
> index a2e11a4..0ea0dd0 100644
> --- a/backend/src/backend/gen_context.cpp
> +++ b/backend/src/backend/gen_context.cpp
> @@ -1911,7 +1911,7 @@ namespace gbe
>      if(sel->isScalarReg(offset.reg()))
>        offset = GenRegister::retype(offset, GEN_TYPE_UW);
>      else
> -      offset = GenRegister::unpacked_uw(offset.nr, offset.subnr /
> typeSize(GEN_TYPE_UW));
> +      offset = GenRegister::unpacked_uw(offset);
>      uint32_t baseRegOffset = GenRegister::grfOffset(baseReg);
>      //There is a restrict that: lower 5 bits indirect reg SubRegNum and
>      //the lower 5 bits of indirect imm SubRegNum cannot exceed 5 bits.
> diff --git a/backend/src/backend/gen_register.hpp
> b/backend/src/backend/gen_register.hpp
> index aa0744b..bbea761 100644
> --- a/backend/src/backend/gen_register.hpp
> +++ b/backend/src/backend/gen_register.hpp
> @@ -956,6 +956,16 @@ namespace gbe
>                      GEN_HORIZONTAL_STRIDE_0);
>      }
> 
> +    static INLINE uint32_t hstrideFromSize(int size) {
> +      switch (size) {
> +        case 0: return GEN_HORIZONTAL_STRIDE_0;
> +        case 1: return GEN_HORIZONTAL_STRIDE_1;
> +        case 2: return GEN_HORIZONTAL_STRIDE_2;
> +        case 4: return GEN_HORIZONTAL_STRIDE_4;
> +        default: NOT_IMPLEMENTED; return GEN_HORIZONTAL_STRIDE_0;
> +      }
> +    }
> +
>      static INLINE int hstride_size(GenRegister reg) {
>        switch (reg.hstride) {
>          case GEN_HORIZONTAL_STRIDE_0: return 0;
> @@ -1193,6 +1203,22 @@ namespace gbe
>                           GEN_HORIZONTAL_STRIDE_2);
>      }
> 
> +    static INLINE GenRegister unpacked_uw(const GenRegister& reg) {
> +      uint32_t nr = reg.nr;
> +      uint32_t subnr = reg.subnr / typeSize(GEN_TYPE_UW);
> +      uint32_t width = reg.width;
> +      int hstrideSize = GenRegister::hstride_size(reg) * typeSize(reg.type) /
> typeSize(GEN_TYPE_UW);
> +      uint32_t hstride = GenRegister::hstrideFromSize(hstrideSize);
> +
> +      return GenRegister(GEN_GENERAL_REGISTER_FILE,
> +                         nr,
> +                         subnr,
> +                         GEN_TYPE_UW,
> +                         GEN_VERTICAL_STRIDE_16,
> +                         width,
> +                         hstride);
> +    }
> +
>      static INLINE GenRegister packed_ud(uint32_t nr, uint32_t subnr) {
>        return GenRegister(GEN_GENERAL_REGISTER_FILE,
>                           nr,
> --
> 1.9.1
> 
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