[Beignet] [PATCH 1/2] SKL: fix some 3D and 2D array image fail.

[Yang Rong]

SKL need use aligned_pitch * aligned_h to calculate slice pitch, so add a new type of
cl_buffer_get_tiling_align to get it.

Signed-off-by: Yang Rong <rong.r.yang at intel.com>
---
 src/cl_mem.c             |  3 ++-
 src/intel/intel_driver.c | 16 +++++++++++++++-
 src/intel/intel_gpgpu.c  |  4 ++--
 3 files changed, 19 insertions(+), 4 deletions(-)

diff --git a/src/cl_mem.c b/src/cl_mem.c
index e91d608..153bc27 100644
--- a/src/cl_mem.c
+++ b/src/cl_mem.c
@@ -843,7 +843,8 @@ _cl_mem_new_image(cl_context ctx,
       image_type == CL_MEM_OBJECT_IMAGE1D_BUFFER)
     aligned_slice_pitch = 0;
   else
-    aligned_slice_pitch = aligned_pitch * ALIGN(h, cl_buffer_get_tiling_align(ctx, CL_NO_TILE, 1));
+    //SKL need use tiling's aligned_h to calc slice_pitch and IVB to BDW need CL_NO_TILE's aligned_h to calc.
+    aligned_slice_pitch = aligned_pitch * ALIGN(h, cl_buffer_get_tiling_align(ctx, tiling, 2));
 
   cl_mem_image_init(cl_mem_image(mem), w, h, image_type, depth, *fmt,
                     intel_fmt, bpp, aligned_pitch, aligned_slice_pitch, tiling,
diff --git a/src/intel/intel_driver.c b/src/intel/intel_driver.c
index afa4486..1862021 100644
--- a/src/intel/intel_driver.c
+++ b/src/intel/intel_driver.c
@@ -464,6 +464,13 @@ static uint32_t intel_buffer_get_tiling_align(cl_context ctx, uint32_t tiling_mo
       ret = 512;
     } else if (dim == 1) { //tileX height in number of rows
       ret = 8;
+    }  else if (dim == 2) { //height to calculate slice pitch
+      if (gen_ver == 9) //SKL same as tileY height
+        ret = 8;
+      else if (gen_ver == 8)  //IVB, HSW, BDW same as CL_NO_TILE vertical alignment
+        ret = 4;
+      else
+        ret = 2;
     } else
       assert(0);
     break;
@@ -473,12 +480,19 @@ static uint32_t intel_buffer_get_tiling_align(cl_context ctx, uint32_t tiling_mo
       ret = 128;
     } else if (dim == 1) { //tileY height in number of rows
       ret = 32;
+    } else if (dim == 2) { //height to calculate slice pitch
+      if (gen_ver == 9) //SKL same as tileY height
+        ret = 32;
+      else if (gen_ver == 8) //IVB, HSW, BDW same as CL_NO_TILE vertical alignment
+        ret = 4;
+      else
+        ret = 2;
     } else
       assert(0);
     break;
 
   case CL_NO_TILE:
-    if (dim == 1) { //vertical alignment
+    if (dim == 1 || dim == 2) { //vertical alignment
       if (gen_ver == 8 || gen_ver == 9) //SKL 1D array need 4 alignment qpitch
         ret = 4;
       else
diff --git a/src/intel/intel_gpgpu.c b/src/intel/intel_gpgpu.c
index 36f6eef..177ac04 100644
--- a/src/intel/intel_gpgpu.c
+++ b/src/intel/intel_gpgpu.c
@@ -1344,11 +1344,11 @@ intel_gpgpu_bind_image_gen9(intel_gpgpu_t *gpgpu,
 
   if (intel_is_surface_array(type) && ss->ss0.surface_type == I965_SURFACE_2D) {
     ss->ss0.surface_array = 1;
-    ss->ss1.surface_qpitch = (h + 3)/4;
+    ss->ss1.surface_qpitch = (slice_pitch/pitch + 3)/4;
   }
 
   if(ss->ss0.surface_type == I965_SURFACE_3D)
-    ss->ss1.surface_qpitch = (h + 3)/4;
+    ss->ss1.surface_qpitch = (slice_pitch/pitch + 3)/4;
 
   ss->ss0.horizontal_alignment = 1;
   ss->ss0.vertical_alignment = 1;
-- 
1.8.3.2