[Beignet] [PATCH 03/27] Add long imm value in gen8 instruction.

[junyan.he at inbox.com]

From: Junyan He <junyan.he at linux.intel.com>

gen8 now support 64 bits immediate value for
one src instruction.

Signed-off-by: Junyan He <junyan.he at linux.intel.com>
---
 backend/src/backend/gen8_encoder.cpp     | 14 +++++++++-----
 backend/src/backend/gen8_instruction.hpp |  2 ++
 2 files changed, 11 insertions(+), 5 deletions(-)

diff --git a/backend/src/backend/gen8_encoder.cpp b/backend/src/backend/gen8_encoder.cpp
index ae2d4eb..8d4b74f 100644
--- a/backend/src/backend/gen8_encoder.cpp
+++ b/backend/src/backend/gen8_encoder.cpp
@@ -331,11 +331,15 @@ namespace gbe
       gen8_insn->bits2.da1.src0_negate = reg.negation;
       gen8_insn->bits2.da1.src0_address_mode = reg.address_mode;
       if (reg.file == GEN_IMMEDIATE_VALUE) {
-        gen8_insn->bits3.ud = reg.value.ud;
-
-        /* Required to set some fields in src1 as well: */
-        gen8_insn->bits2.da1.src1_reg_file = 0; /* arf */
-        gen8_insn->bits2.da1.src1_reg_type = reg.type;
+        if (reg.type == GEN_TYPE_L || reg.type == GEN_TYPE_UL) {
+          gen8_insn->bits3.ud = (uint32_t)(reg.value.i64 >> 32);
+          gen8_insn->bits2.ud = (uint32_t)(reg.value.i64);
+        } else {
+          gen8_insn->bits3.ud = reg.value.ud;
+          /* Required to set some fields in src1 as well: */
+          gen8_insn->bits2.da1.src1_reg_file = 0; /* arf */
+          gen8_insn->bits2.da1.src1_reg_type = reg.type;
+        }
       }
       else {
         if (gen8_insn->header.access_mode == GEN_ALIGN_1) {
diff --git a/backend/src/backend/gen8_instruction.hpp b/backend/src/backend/gen8_instruction.hpp
index 8981fe7..48f9795 100644
--- a/backend/src/backend/gen8_instruction.hpp
+++ b/backend/src/backend/gen8_instruction.hpp
@@ -232,6 +232,8 @@ union Gen8NativeInstruction
       struct {
         uint32_t uip:32;
       } gen8_branch;
+
+      uint32_t ud;
     } bits2;
 
     union {
-- 
1.9.1