[Beignet] [PATCH 13/27] Add the handleLong virtual function into gen encoder

junyan.he at inbox.com junyan.he at inbox.com
Tue Jan 6 02:01:33 PST 2015


From: Junyan He <junyan.he at linux.intel.com>

This function is used to handle the common cases for
ALU1 and ALU2 operations. If native long is not supported,
this function will split the src and dst into top half
and bottom half, else it just return false.
So far, just ALU1 function will use it.

Signed-off-by: Junyan He <junyan.he at linux.intel.com>
---
 backend/src/backend/gen8_encoder.cpp |  5 +++++
 backend/src/backend/gen8_encoder.hpp |  2 ++
 backend/src/backend/gen_encoder.cpp  | 14 +++++++++++---
 backend/src/backend/gen_encoder.hpp  |  4 +++-
 4 files changed, 21 insertions(+), 4 deletions(-)

diff --git a/backend/src/backend/gen8_encoder.cpp b/backend/src/backend/gen8_encoder.cpp
index 8d4b74f..33bb802 100644
--- a/backend/src/backend/gen8_encoder.cpp
+++ b/backend/src/backend/gen8_encoder.cpp
@@ -413,6 +413,11 @@ namespace gbe
     }
   }
 
+  bool Gen8Encoder::handleLong(uint32_t opcode, GenRegister dst, GenRegister src0, GenRegister src1)
+  {
+    return false;
+  }
+
 #define NO_SWIZZLE ((0<<0) | (1<<2) | (2<<4) | (3<<6))
 
   void Gen8Encoder::alu3(uint32_t opcode,
diff --git a/backend/src/backend/gen8_encoder.hpp b/backend/src/backend/gen8_encoder.hpp
index e0d934f..6bad3ff 100644
--- a/backend/src/backend/gen8_encoder.hpp
+++ b/backend/src/backend/gen8_encoder.hpp
@@ -63,6 +63,8 @@ namespace gbe
     virtual bool disableCompact() { return true; }
     virtual void alu3(uint32_t opcode, GenRegister dst,
                        GenRegister src0, GenRegister src1, GenRegister src2);
+    virtual bool handleLong(uint32_t opcode, GenRegister dst, GenRegister src0,
+                            GenRegister src1 = GenRegister::null());
   };
 }
 #endif /* __GBE_GEN8_ENCODER_HPP__ */
diff --git a/backend/src/backend/gen_encoder.cpp b/backend/src/backend/gen_encoder.cpp
index d21bece..3e22b1d 100644
--- a/backend/src/backend/gen_encoder.cpp
+++ b/backend/src/backend/gen_encoder.cpp
@@ -488,6 +488,14 @@ namespace gbe
      return (GenNativeInstruction *)(&this->store.back()-1);
   }
 
+  bool GenEncoder::handleLong(uint32_t opcode, GenRegister dst, GenRegister src0, GenRegister src1)
+  {
+	/* By now, just alu1 insn will come to here. So just MOV */
+    this->MOV(dst.bottom_half(), src0.bottom_half());
+    this->MOV(dst.top_half(this->simdWidth), src0.top_half(this->simdWidth));
+    return true;
+  }
+
   INLINE void _handleDouble(GenEncoder *p, uint32_t opcode, GenRegister dst,
                             GenRegister src0, GenRegister src1 = GenRegister::null()) {
        int w = p->curr.execWidth;
@@ -537,9 +545,9 @@ namespace gbe
             GenRegister src, uint32_t condition) {
      if (dst.isdf() && src.isdf()) {
        handleDouble(p, opcode, dst, src);
-     } else if (dst.isint64() && src.isint64()) { // handle int64
-       p->MOV(dst.bottom_half(), src.bottom_half());
-       p->MOV(dst.top_half(p->simdWidth), src.top_half(p->simdWidth));
+     } else if (dst.isint64() && src.isint64()
+                && p->handleLong(opcode, dst, src)) { // handle int64
+       return;
      } else if (needToSplitAlu1(p, dst, src) == false) {
       if(compactAlu1(p, opcode, dst, src, condition, false))
         return;
diff --git a/backend/src/backend/gen_encoder.hpp b/backend/src/backend/gen_encoder.hpp
index 97d6258..49d307f 100644
--- a/backend/src/backend/gen_encoder.hpp
+++ b/backend/src/backend/gen_encoder.hpp
@@ -229,8 +229,10 @@ namespace gbe
     virtual bool disableCompact() { return false; }
     GenNativeInstruction *next(uint32_t opcode);
     uint32_t n_instruction(void) const { return store.size(); }
-    GBE_CLASS(GenEncoder); //!< Use custom allocators
+    virtual bool handleLong(uint32_t opcode, GenRegister dst, GenRegister src0,
+                            GenRegister src1 = GenRegister::null());
 
+    GBE_CLASS(GenEncoder); //!< Use custom allocators
     virtual void alu3(uint32_t opcode, GenRegister dst,
                        GenRegister src0, GenRegister src1, GenRegister src2) = 0;
   };
-- 
1.9.1



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