[Beignet] [PATCH 1/3] add LZD IR instruction.

[xionghu.luo at intel.com]

From: Luo Xionghu <xionghu.luo at intel.com>

the LZD IR instruction was missed, should be enabled to generate harware
supported instruction.

v2: add gen backend implementation.

Signed-off-by: Luo Xionghu <xionghu.luo at intel.com>
---
 backend/src/backend/gen_context.cpp        | 1 +
 backend/src/backend/gen_insn_selection.cpp | 3 ++-
 backend/src/ir/instruction.cpp             | 1 +
 backend/src/ir/instruction.hpp             | 2 ++
 backend/src/ir/instruction.hxx             | 1 +
 backend/src/llvm/llvm_gen_backend.cpp      | 9 +++++++++
 6 files changed, 16 insertions(+), 1 deletion(-)

diff --git a/backend/src/backend/gen_context.cpp b/backend/src/backend/gen_context.cpp
index 3fab9c8..1912d0e 100644
--- a/backend/src/backend/gen_context.cpp
+++ b/backend/src/backend/gen_context.cpp
@@ -206,6 +206,7 @@ namespace gbe
       case SEL_OP_FBH: p->FBH(dst, src); break;
       case SEL_OP_FBL: p->FBL(dst, src); break;
       case SEL_OP_CBIT: p->CBIT(dst, src); break;
+      case SEL_OP_LZD: p->LZD(dst, src); break;
       case SEL_OP_NOT: p->NOT(dst, src); break;
       case SEL_OP_RNDD: p->RNDD(dst, src); break;
       case SEL_OP_RNDU: p->RNDU(dst, src); break;
diff --git a/backend/src/backend/gen_insn_selection.cpp b/backend/src/backend/gen_insn_selection.cpp
index f83edf5..a134a1e 100644
--- a/backend/src/backend/gen_insn_selection.cpp
+++ b/backend/src/backend/gen_insn_selection.cpp
@@ -1942,7 +1942,7 @@ namespace gbe
     static ir::Type getType(const ir::Opcode opcode, const ir::Type insnType) {
       if (insnType == ir::TYPE_S64 || insnType == ir::TYPE_U64 || insnType == ir::TYPE_S8 || insnType == ir::TYPE_U8)
         return insnType;
-      if (opcode == ir::OP_FBH || opcode == ir::OP_FBL || opcode == ir::OP_CBIT)
+      if (opcode == ir::OP_FBH || opcode == ir::OP_FBL || opcode == ir::OP_CBIT || opcode == ir::OP_LZD)
         return ir::TYPE_U32;
       if (insnType == ir::TYPE_S16 || insnType == ir::TYPE_U16)
         return insnType;
@@ -1997,6 +1997,7 @@ namespace gbe
           case ir::OP_FBH: sel.FBH(dst, src); break;
           case ir::OP_FBL: sel.FBL(dst, src); break;
           case ir::OP_CBIT: sel.CBIT(dst, src); break;
+          case ir::OP_LZD: sel.LZD(dst, src); break;
           case ir::OP_COS: sel.MATH(dst, GEN_MATH_FUNCTION_COS, src); break;
           case ir::OP_SIN: sel.MATH(dst, GEN_MATH_FUNCTION_SIN, src); break;
           case ir::OP_LOG: sel.MATH(dst, GEN_MATH_FUNCTION_LOG, src); break;
diff --git a/backend/src/ir/instruction.cpp b/backend/src/ir/instruction.cpp
index 82e7dda..4d1ae05 100644
--- a/backend/src/ir/instruction.cpp
+++ b/backend/src/ir/instruction.cpp
@@ -1594,6 +1594,7 @@ DECL_MEM_FN(GetImageInfoInstruction, uint8_t, getImageIndex(void), getImageIndex
   DECL_EMIT_FUNCTION(FBH)
   DECL_EMIT_FUNCTION(FBL)
   DECL_EMIT_FUNCTION(CBIT)
+  DECL_EMIT_FUNCTION(LZD)
   DECL_EMIT_FUNCTION(COS)
   DECL_EMIT_FUNCTION(SIN)
   DECL_EMIT_FUNCTION(LOG)
diff --git a/backend/src/ir/instruction.hpp b/backend/src/ir/instruction.hpp
index 47312f5..484e7d1 100644
--- a/backend/src/ir/instruction.hpp
+++ b/backend/src/ir/instruction.hpp
@@ -586,6 +586,8 @@ namespace ir {
   Instruction FBL(Type type, Register dst, Register src);
   /*! cbit.type dst src */
   Instruction CBIT(Type type, Register dst, Register src);
+  /*! lzd.type dst src */
+  Instruction LZD(Type type, Register dst, Register src);
   /*! hadd.type dst src */
   Instruction HADD(Type type, Register dst, Register src0, Register src1);
   /*! rhadd.type dst src */
diff --git a/backend/src/ir/instruction.hxx b/backend/src/ir/instruction.hxx
index 9a89069..b52673e 100644
--- a/backend/src/ir/instruction.hxx
+++ b/backend/src/ir/instruction.hxx
@@ -87,6 +87,7 @@ DECL_INSN(I64_MUL_HI, BinaryInstruction)
 DECL_INSN(FBH, UnaryInstruction)
 DECL_INSN(FBL, UnaryInstruction)
 DECL_INSN(CBIT, UnaryInstruction)
+DECL_INSN(LZD, UnaryInstruction)
 DECL_INSN(HADD, BinaryInstruction)
 DECL_INSN(RHADD, BinaryInstruction)
 DECL_INSN(I64HADD, BinaryInstruction)
diff --git a/backend/src/llvm/llvm_gen_backend.cpp b/backend/src/llvm/llvm_gen_backend.cpp
index 8d22c4e..a73f9e8 100644
--- a/backend/src/llvm/llvm_gen_backend.cpp
+++ b/backend/src/llvm/llvm_gen_backend.cpp
@@ -2790,6 +2790,7 @@ error:
           case Intrinsic::umul_with_overflow:
             this->newRegister(&I);
           break;
+          case Intrinsic::ctlz:
           case Intrinsic::bswap:
             this->newRegister(&I);
           break;
@@ -3203,6 +3204,14 @@ error:
             }
           }
           break;
+          case Intrinsic::ctlz:
+          {
+            ir::Type srcType = getType(ctx, I.getType());
+            const ir::Register dst = this->getRegister(&I);
+            const ir::Register src = this->getRegister(I.getOperand(0));
+            ctx.ALU1(ir::OP_LZD, srcType, dst, src);
+          }
+          break;
           default: NOT_IMPLEMENTED;
         }
       } else {
-- 
1.9.1